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| author | Ian Chao <mlchao@nuvoton.com> | 2015-07-09 14:53:00 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-25 01:22:32 +0000 |
| commit | 14bd917343489c09033f0f9c97e7951d5cb2aeec (patch) | |
| tree | 1722f9d92f5ffb2525eebec68f86b1aab06b3e71 /core | |
| parent | 7de0037538bd0016c9202ad289655cbf4f4d90aa (diff) | |
| download | chrome-ec-14bd917343489c09033f0f9c97e7951d5cb2aeec.tar.gz | |
nuc:
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/task.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 09d7108e7b..9f275391d3 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -66,11 +66,30 @@ extern int __task_start(int *task_stack_ready); void __idle(void) { while (1) { +#ifdef CHIP_NPCX + /* + * TODO (ML): A interrupt that occurs shortly before entering + * idle mode starts getting services while the Core transitions + * into idle mode. The results in a hard fault when the Core, + * shortly therefore, resumes execution on exiting idle mode. + * Workaround: Replace the idle function with the followings + */ + asm ( + "cpsid i\n" /* Disable interrupt */ + "push {r0-r5}\n" /* Save needed registers */ + "ldr r0, =0x100A8000\n" /* Set r0 to a valid RAM addr */ + "wfi\n" /* Wait for int to enter idle */ + "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ + "pop {r0-r5}\n" /* Restore regs before enabling ints */ + "cpsie i\n" /* Enable interrupts */ + ); +#else /* * Wait for the next irq event. This stops the CPU clock * (sleep / deep sleep, depending on chip config). */ asm("wfi"); +#endif } } #endif /* !CONFIG_LOW_POWER_IDLE */ |