Revert "cortex-m: add D-cache support"

This reverts commit edbfb3a43b6c4e1dd28f6d00a59896cae198f68b.

BUG=b:200823466
TEST=make buildall -j

Change-Id: Iafdc81e9cb1593fea49ffcce1577edd7b5a14b1b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3273421
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>

4 files changed, 6 insertions, 97 deletions

diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index 2d78a9dc46..d352174dd4 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -37,7 +37,6 @@ endif
 core-y=cpu.o init.o ldivmod.o llsr.o uldivmod.o vecttable.o
 core-$(CONFIG_AES)+=aes.o
 core-$(CONFIG_AES_GCM)+=ghash.o
-core-$(CONFIG_ARMV7M_CACHE)+=cache.o
 core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o
 core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o
 core-$(CONFIG_WATCHDOG)+=watchdog.o
diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S
deleted file mode 100644
index 0a3d3bb67d..0000000000
--- a/core/cortex-m/cache.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * ARMv7-M architectural caches maintenance operations.
- */
-
-.syntax unified
-.text
-.thumb
-
-/* System Control Block: cache registers */
-#define SCB_CCSIDR 0xe000ed80
-#define SCB_CCSELR 0xe000ed84
-#define SCB_DCISW  0xe000ef60
-#define SCB_DCCISW 0xe000ef74
-
-.macro dcache_set_way_op name register
-@
-@ Perform an operation on all D-cache sets/ways.
-@
-@ Note: implemented in assembly to guarantee that we are not touching the
-@ D-cache in the middle of the loop.
-@
-.thumb_func
-.section .text.\name
-.global \name
-\name:
-	/* Select Level-1 Data cache (for operations on CCSIDR). */
-	ldr  r1, =SCB_CCSELR
-	movs r0, #0
-	ldr  r2, =SCB_CCSIDR
-	str  r0, [r1]  /* set CCSELR = 0 */
-
-	/* Ensure the CCSELR write is effective before reading CCSIDR. */
-	dsb
-	/* CCSIDR contains the cache geometry. */
-	ldr  r3, [r2]  /* [27:13] Number of sets -1  [12:3] Number of ways -1 */
-
-	/* register used to do the set/way cache operation. */
-	ldr  r0, =\register
-	/* r2 is the number of cache 'sets' - 1 */
-	ubfx r2, r3, #13, #15
-	/* r12 is the number of cache 'ways' - 1 */
-	ubfx r12, r3, #3, #10
-
-1:
-	mov  r1, r12    /* reset way index */
-2:
-	/*
-	 * Build address Set/Way operation e.g DC(C)ISW
-	 * [31:30] way index [13:5] set index
-	 */
-	lsls r3, r2, #5 /* set index */
-	/* TODO(crbug.com/848704) remove cache geometry assumptions */
-	orr  r3, r3, r1, lsl #30 /* way index */
-	/* Perform operation (e.g invalidate) on a D-cache line */
-	str  r3, [r0]
-	/* go to previous way */
-	subs r1, #1
-	bcs  2b
-	/* go to previous set */
-	subs r2, #1
-	bcs  1b
-
-	/* Ensure everything has propagated and return. */
-	dsb
-	isb
-	bx  lr
-.endm
-
-/* D-cache Invalidate by set-way */
-dcache_set_way_op cpu_invalidate_dcache SCB_DCISW
-
-/* D-cache Clean and Invalidate by set-way, to Point of Coherency */
-dcache_set_way_op cpu_clean_invalidate_dcache SCB_DCCISW
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c
index 96ac96a016..bd5b6bd3a7 100644
--- a/core/cortex-m/cpu.c
+++ b/core/cortex-m/cpu.c
@@ -30,7 +30,7 @@ static void cpu_invalidate_icache(void)
 	asm volatile("dsb; isb");
 }
 
-void cpu_enable_caches(void)
+void cpu_enable_icache(void)
 {
 	/* Check whether the I-cache is already enabled */
 	if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_ICACHE)) {
@@ -40,25 +40,16 @@ void cpu_enable_caches(void)
 		CPU_NVIC_CCR |= CPU_NVIC_CCR_ICACHE;
 		asm volatile("dsb; isb");
 	}
-	/* Check whether the D-cache is already enabled */
-	if (!(CPU_NVIC_CCR & CPU_NVIC_CCR_DCACHE)) {
-		/* Invalidate the D-cache first */
-		cpu_invalidate_dcache();
-		/* Turn on the caching */
-		CPU_NVIC_CCR |= CPU_NVIC_CCR_DCACHE;
-		asm volatile("dsb; isb");
-	}
 }
 
 static void cpu_sysjump_cache(void)
 {
 	/*
-	 * Disable the I-cache and the D-cache
-	 * The I-cache will be invalidated after the sysjump if needed
+	 * Disable the I-cache
+	 * so we will invalidate it after the sysjump if needed
 	 * (e.g after a flash update).
 	 */
-	cpu_clean_invalidate_dcache();
-	CPU_NVIC_CCR &= ~(CPU_NVIC_CCR_ICACHE | CPU_NVIC_CCR_DCACHE);
+	CPU_NVIC_CCR &= ~CPU_NVIC_CCR_ICACHE;
 	asm volatile("dsb; isb");
 }
 DECLARE_HOOK(HOOK_SYSJUMP, cpu_sysjump_cache, HOOK_PRIO_LAST);
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index 504a0ca8df..ce9f2ac66b 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -61,16 +61,11 @@ enum {
 #define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
 #define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
 #define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
-/* Enable the CPU I-cache and D-cache if they are not already enabled */
-void cpu_enable_caches(void);
-/* Invalidate the D-cache */
-void cpu_invalidate_dcache(void);
-/* Clean and Invalidate the D-cache to the Point of Coherency */
-void cpu_clean_invalidate_dcache(void);
+/* Enable the CPU instruction cache if it is not already enabled */
+void cpu_enable_icache(void);
 
 /* Invalidate a single address of the D-cache */
 void cpu_invalidate_dcache_address(uintptr_t address);