diff options
| author | Dino Li <dino.li@ite.com.tw> | 2015-07-02 17:05:51 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-08 09:25:48 +0000 |
| commit | a69c63bae5223b6a0070ee2ab48b6c9db65dc6c7 (patch) | |
| tree | 45adb050cb7fc959f672a1413eec5677c394c3c1 /core | |
| parent | d6a6c927248ce16c9467dfa3f170349520cc5bc9 (diff) | |
| download | chrome-ec-a69c63bae5223b6a0070ee2ab48b6c9db65dc6c7.tar.gz | |
it8380dev: add flash module and fix system jump
1. Add flash control module for emulation board.
2. Fix system jump for Andes core.
3. Change the physical size of the flash on the chip to 256KB.
note:
1. Only IT839x series supports flash write protect by registers.
2. Static DMA method of flash code only for IT839x series and IT838x Dx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command flashwp and flashinfo
1-a. flashwp enable
1-b. WP asserted and reboot
1-c. flashinfo RO protected now
1-d. WP deasserted and reboot
1-e. No protected
1-f. flashwp disable
1-g. WP asserted and reboot
1-h. No protected
2. console sysjump and sysinfo
2-a. sysjump rw
2-b. jumping to image RW
2-c. sysinfo, Copy : RW, Jumped : yes
2-d. sysjump ro
2-e. jumping to image RO
2-f. sysinfo, Copy : RO, Jumped : yes
3. RO/RW firmware image test
3-a. sysjump rw
3-b. use console command "eflash" to erase RO region,
erase OK and system still work.
3-c. reflash firmware
3-d. sysjump rw, sysjump ro
3-e. use console command "eflash" to erase RW region,
erase OK and system still work.
Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8
Reviewed-on: https://chromium-review.googlesource.com/271390
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Diffstat (limited to 'core')
| -rw-r--r-- | core/nds32/cpu.c | 8 | ||||
| -rw-r--r-- | core/nds32/ec.lds.S | 5 |
2 files changed, 13 insertions, 0 deletions
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c index 545e930eca..bf49a58b2e 100644 --- a/core/nds32/cpu.c +++ b/core/nds32/cpu.c @@ -6,8 +6,16 @@ */ #include "cpu.h" +#include "registers.h" void cpu_init(void) { /* DLM initialization is done in init.S */ + + uint32_t image_type = (uint32_t)cpu_init; + + /* To change interrupt vector base if at RW image */ + if (image_type > CONFIG_RW_MEM_OFF) + /* Interrupt Vector Table Base Address, in 64k Byte unit */ + IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF; } diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 57cf6512d3..a936e72d62 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -37,6 +37,11 @@ SECTIONS KEEP(OUTDIR/core/CORE/init.o (.text.vectirq)) KEEP(OUTDIR/core/CORE/init.o (.text)) *(.text*) + + . = ALIGN(CONFIG_IT83XX_ILM_BLOCK_SIZE); + __flash_dma_start = .; + KEEP(*(.flash_direct_map)) + . = ALIGN(CONFIG_IT83XX_ILM_BLOCK_SIZE); #ifdef COMPILE_FOR_RAM } > IRAM #else |