Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper --relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware- fpmcu-bloonchipper-release Relevant changes: git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint util/getversion.sh ded9307b79 util/getversion.sh: Fix version when not in a git repo 956055e692 board: change Google USB vendor info 71b2ef709d Update license boilerplate text in source code files 33e11afda0 Revert "fpsensor: Build fpsensor source file with C++" c8d0360723 fpsensor: Build fpsensor source file with C++ bc113abd53 fpsensor: Fix g++ compiler error 150a58a0dc fpsensor: Fix fp_set_sensor_mode return type b33b5ce85b fpsensor: Remove nested designators for C++ compatibility 2e864b2539 tree-wide: const-ify argv for console commands 56d8b360f9 test: Add test for get ikm failure when seed not set 3a3d6c3690 test: Add test for fpsensor trivial key failure 233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256 0a041b285b docs/fingerprint: Typo correction c03fab67e2 docs/fingerprint: Fix the path of fputils.py 0b5d4baf5a util/getversion.sh: Fix empty file list handling 6e128fe760 FPMCU dev board environment with Satlab 3eb29b6aa5 builtin: Move ssize_t to sys/types.h 345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release c25ffdb316 common: Conditionally support printf %l and %i modifiers 9a3c514b45 test: Add a test to check if the debugger is connected 54e603413f Move standard library tests to their own file 43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release 25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format 4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format 738de2b575 trng: Rename rand to trng_rand 14b8270edd docs/fingerprint: Update dragonclaw power numbers 0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format 5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format 6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format 7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format 21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format 98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format 73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format 0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format 1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format dc3e9008b8 board/hatch_fp/board.h: Format with clang-format dca9d74321 Revert "trng: Rename rand to trng_rand" a6b0b3554f trng: Rename rand to trng_rand 28d0b75b70 third_party/boringssl: Remove unused header BRANCH=None BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210 BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908 BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158 BUG=b:234781655 b:215613183 b:242720910 TEST=`make -j buildall` TEST=./test/run_device_tests.py --board bloonchipper Test "aes": PASSED Test "cec": PASSED Test "cortexm_fpu": PASSED Test "crc": PASSED Test "flash_physical": PASSED Test "flash_write_protect": PASSED Test "fpsensor_hw": PASSED Test "fpsensor_spi_ro": PASSED Test "fpsensor_spi_rw": PASSED Test "fpsensor_uart_ro": PASSED Test "fpsensor_uart_rw": PASSED Test "mpu_ro": PASSED Test "mpu_rw": PASSED Test "mutex": PASSED Test "pingpong": PASSED Test "printf": PASSED Test "queue": PASSED Test "rollback_region0": PASSED Test "rollback_region1": PASSED Test "rollback_entropy": PASSED Test "rtc": PASSED Test "sha256": PASSED Test "sha256_unrolled": PASSED Test "static_if": PASSED Test "stdlib": PASSED Test "system_is_locked_wp_on": PASSED Test "system_is_locked_wp_off": PASSED Test "timer_dos": PASSED Test "utils": PASSED Test "utils_str": PASSED Test "stm32f_rtc": PASSED Test "panic_data_bloonchipper_v2.0.4277": PASSED Test "panic_data_bloonchipper_v2.0.5938": PASSED Force-Relevant-Builds: all Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3
author: Tom Hughes <tomhughes@chromium.org> 2022-09-21 14:10:01 -0700
committer: Tom Hughes <tomhughes@chromium.org> 2022-09-22 12:49:33 -0700
commit: 2bcf863b492fe7ed8105c853814dba6ed32ba719 (patch)
tree: fcf6ce5810f9ff9e3c8cce434812dd75492269ed /core
parent: e5fb0b9ba488614b5684e640530f00821ab7b943 (diff)
parent: 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff)
download: chrome-ec-2bcf863b492fe7ed8105c853814dba6ed32ba719.tar.gz
113 files changed, 1265 insertions, 1555 deletions
diff --git a/core/cortex-m/atomic.h b/core/cortex-m/atomic.h
index a09f5cc8be..92ecdd96e5 100644
--- a/core/cortex-m/atomic.h
+++ b/core/cortex-m/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,4 +41,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index bcffe16e8d..1e2c47297b 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -1,24 +1,11 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Cortex-M4 core OS files build
 #
 
-
-ifeq ($(cc-name),gcc)
-# coreboot sdk
-CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
-else
-# llvm sdk
-CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi-
-endif
-
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	$(CROSS_COMPILE_ARM_DEFAULT))
-
 # FPU compilation flags
 CFLAGS_FPU-$(CONFIG_FPU)=-mfloat-abi=hard
 ifeq ($(cc-name),gcc)
diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S
index 0a3d3bb67d..d5089a920e 100644
--- a/core/cortex-m/cache.S
+++ b/core/cortex-m/cache.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/config_core.h b/core/cortex-m/config_core.h
index 0665b28852..949df7ee21 100644
--- a/core/cortex-m/config_core.h
+++ b/core/cortex-m/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c
index 7c31892c18..ffb6b7780c 100644
--- a/core/cortex-m/cpu.c
+++ b/core/cortex-m/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,7 +16,8 @@ void cpu_init(void)
 
 	/* Enable reporting of memory faults, bus faults and usage faults */
 	CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA |
-		CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA;
+			  CPU_NVIC_SHCSR_BUSFAULTENA |
+			  CPU_NVIC_SHCSR_USGFAULTENA;
 }
 
 #ifdef CONFIG_ARMV7M_CACHE
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index e3137cd864..8c284d6132 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,68 +10,69 @@
 
 #include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
-#define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              BIT(0)
-#define ST_TICKINT             BIT(1)
-#define ST_CLKSOURCE           BIT(2)
-#define ST_COUNTFLAG           BIT(16)
+#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010)
+#define ST_ENABLE BIT(0)
+#define ST_TICKINT BIT(1)
+#define ST_CLKSOURCE BIT(2)
+#define ST_COUNTFLAG BIT(16)
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180 + 4 * (x))
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280 + 4 * (x))
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10))
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0xFA05U << 16)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_PRIOGRP (BIT(8) | BIT(9) | BIT(10))
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* NVIC STIR : Software Trigger Interrupt Register */
-#define CPU_NVIC_SWTRIG        CPUREG(0xe000ef00)
+#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
 
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
-#define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
-#define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
-#define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
-#define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
+#define CPU_NVIC_CFSR CPUREG(0xe000ed28)
+#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
+#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
+#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
+#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
 
 enum {
-	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
-	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
+	CPU_NVIC_CFSR_BFARVALID = BIT(15),
+	CPU_NVIC_CFSR_MFARVALID = BIT(7),
 
-	CPU_NVIC_CCR_ICACHE		= BIT(17),
-	CPU_NVIC_CCR_DCACHE		= BIT(16),
-	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
-	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
+	CPU_NVIC_CCR_ICACHE = BIT(17),
+	CPU_NVIC_CCR_DCACHE = BIT(16),
+	CPU_NVIC_CCR_DIV_0_TRAP = BIT(4),
+	CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3),
 
-	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= BIT(30),
-	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
+	CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
+	CPU_NVIC_HFSR_FORCED = BIT(30),
+	CPU_NVIC_HFSR_VECTTBL = BIT(1),
 
-	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
-	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
-	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
+	CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16),
+	CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17),
+	CPU_NVIC_SHCSR_USGFAULTENA = BIT(18),
 };
 
 /* System Control Block: cache registers */
-#define CPU_SCB_CCSIDR         CPUREG(0xe000ed80)
-#define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
-#define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
-#define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
+#define CPU_SCB_CCSIDR CPUREG(0xe000ed80)
+#define CPU_SCB_CCSELR CPUREG(0xe000ed84)
+#define CPU_SCB_ICIALLU CPUREG(0xe000ef50)
+#define CPU_SCB_DCISW CPUREG(0xe000ef60)
+#define CPU_SCB_DCCISW CPUREG(0xe000ef74)
 
 /* Floating Point Context Address Register */
-#define CPU_FPU_FPCAR          CPUREG(0xe000ef38)
+#define CPU_FPU_FPCAR CPUREG(0xe000ef38)
 
 /*
  * As defined by Armv7-M Reference Manual B1.5.7 "Context state stacking on
@@ -85,28 +86,29 @@ enum {
 #define FPU_FPSCR_UFC BIT(3) /* Underflow */
 #define FPU_FPSCR_IXC BIT(4) /* Inexact */
 #define FPU_FPSCR_IDC BIT(7) /* Input denormal */
-#define FPU_FPSCR_EXC_FLAGS (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | \
-			     FPU_FPSCR_UFC | FPU_FPSCR_IXC | FPU_FPSCR_IDC)
+#define FPU_FPSCR_EXC_FLAGS                                              \
+	(FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | FPU_FPSCR_UFC | \
+	 FPU_FPSCR_IXC | FPU_FPSCR_IDC)
 
 /* Bitfield values for EXC_RETURN. */
-#define EXC_RETURN_ES_MASK	BIT(0)
+#define EXC_RETURN_ES_MASK BIT(0)
 #define EXC_RETURN_ES_NON_SECURE 0
-#define EXC_RETURN_ES_SECURE	BIT(0)
-#define EXC_RETURN_SPSEL_MASK	BIT(2)
-#define EXC_RETURN_SPSEL_MSP	0
-#define EXC_RETURN_SPSEL_PSP	BIT(2)
-#define EXC_RETURN_MODE_MASK	BIT(3)
-#define EXC_RETURN_MODE_HANDLER	0
-#define EXC_RETURN_MODE_THREAD	BIT(3)
-#define EXC_RETURN_FTYPE_MASK	BIT(4)
-#define EXC_RETURN_FTYPE_ON	0
-#define EXC_RETURN_FTYPE_OFF	BIT(4)
-#define EXC_RETURN_DCRS_MASK	BIT(5)
-#define EXC_RETURN_DCRS_OFF	0
-#define EXC_RETURN_DCRS_ON	BIT(5)
-#define EXC_RETURN_S_MASK	BIT(6)
-#define EXC_RETURN_S_NON_SECURE	0
-#define EXC_RETURN_S_SECURE	BIT(6)
+#define EXC_RETURN_ES_SECURE BIT(0)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
+#define EXC_RETURN_FTYPE_MASK BIT(4)
+#define EXC_RETURN_FTYPE_ON 0
+#define EXC_RETURN_FTYPE_OFF BIT(4)
+#define EXC_RETURN_DCRS_MASK BIT(5)
+#define EXC_RETURN_DCRS_OFF 0
+#define EXC_RETURN_DCRS_ON BIT(5)
+#define EXC_RETURN_S_MASK BIT(6)
+#define EXC_RETURN_S_NON_SECURE 0
+#define EXC_RETURN_S_SECURE BIT(6)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
@@ -132,10 +134,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 7)
 		priority = 7;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(7 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(7 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m/debug.c b/core/cortex-m/debug.c
index db8891b5d8..214e8dd177 100644
--- a/core/cortex-m/debug.c
+++ b/core/cortex-m/debug.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h
index ae5ef08d06..30643268cb 100644
--- a/core/cortex-m/debug.h
+++ b/core/cortex-m/debug.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index f85b262c18..8580e366b7 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -309,6 +309,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -457,6 +461,12 @@ SECTIONS
 		__data_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated
 		 * RAM, so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/cortex-m/fpu.c b/core/cortex-m/fpu.c
index 29fa568fd8..6e897a5266 100644
--- a/core/cortex-m/fpu.c
+++ b/core/cortex-m/fpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "hooks.h"
 #include "task.h"
 
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ##args)
 
 /* Floating point unit common code */
 
@@ -65,8 +65,7 @@ static void fpu_warn(void)
 
 DECLARE_DEFERRED(fpu_warn);
 
-test_mockable
-void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp)
+test_mockable void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp)
 {
 	/*
 	 * Get address of exception FPU exception frame. FPCAR register points
diff --git a/core/cortex-m/include/fpu.h b/core/cortex-m/include/fpu.h
index 0949d336e2..74862d00ab 100644
--- a/core/cortex-m/include/fpu.h
+++ b/core/cortex-m/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,16 @@
 static inline float sqrtf(float v)
 {
 	float root;
-	asm volatile(
-		"fsqrts %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
+	asm volatile("fsqrts %0, %1" : "=w"(root) : "w"(v));
 	return root;
 }
 
 static inline float fabsf(float v)
 {
 	float root;
-	asm volatile(
-		"fabss %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
+	asm volatile("fabss %0, %1" : "=w"(root) : "w"(v));
 	return root;
 }
-#endif  /* CONFIG_FPU */
+#endif /* CONFIG_FPU */
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h
index 610728b501..75f95e7000 100644
--- a/core/cortex-m/include/mpu.h
+++ b/core/cortex-m/include/mpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 /*
  * ARMv7-M SRAM region
  */
-#define CORTEX_M_SRAM_BASE	0x20000000
+#define CORTEX_M_SRAM_BASE 0x20000000
 
 /*
  * Region assignment. 7 as the highest, a higher index has a higher priority.
@@ -26,64 +26,64 @@
  * made mutually exclusive.
  */
 enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
+	REGION_DATA_RAM = 0, /* For internal data RAM */
+	REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
+	REGION_CODE_RAM = 2, /* For internal code RAM */
+	REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
+	REGION_STORAGE = 4, /* For mapped internal storage */
+	REGION_STORAGE2 = 5, /* Second region for unaligned size */
+	REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
+	REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
 	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
+	REGION_UNCACHED_RAM = 8, /* For uncached data RAM */
+	REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */
+	REGION_ROLLBACK = 10, /* For rollback */
 };
 
-#define MPU_TYPE		REG32(0xe000ed90)
-#define MPU_CTRL		REG32(0xe000ed94)
-#define MPU_NUMBER		REG32(0xe000ed98)
-#define MPU_BASE		REG32(0xe000ed9c)
-#define MPU_SIZE		REG16(0xe000eda0)
-#define MPU_ATTR		REG16(0xe000eda2)
+#define MPU_TYPE REG32(0xe000ed90)
+#define MPU_CTRL REG32(0xe000ed94)
+#define MPU_NUMBER REG32(0xe000ed98)
+#define MPU_BASE REG32(0xe000ed9c)
+#define MPU_SIZE REG16(0xe000eda0)
+#define MPU_ATTR REG16(0xe000eda2)
 
 /*
  * See ARM v7-M Architecture Reference Manual
  * Section B3.5.5 MPU Type Register, MPU_TYPE
  */
-#define MPU_TYPE_UNIFIED_MASK	0x00FF0001
-#define MPU_TYPE_REG_COUNT(t)	(((t) >> 8) & 0xFF)
+#define MPU_TYPE_UNIFIED_MASK 0x00FF0001
+#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF)
 
-#define MPU_CTRL_PRIVDEFEN	BIT(2)
-#define MPU_CTRL_HFNMIENA	BIT(1)
-#define MPU_CTRL_ENABLE		BIT(0)
+#define MPU_CTRL_PRIVDEFEN BIT(2)
+#define MPU_CTRL_HFNMIENA BIT(1)
+#define MPU_CTRL_ENABLE BIT(0)
 
 /*
  * Minimum region size is 32 bytes, 5 bits of address space
  */
-#define MPU_SIZE_BITS_MIN	5
+#define MPU_SIZE_BITS_MIN 5
 
 /*
  * XN (execute never) bit. It's bit 12 if accessed by halfword.
  *   0: XN off
  *   1: XN on
  */
-#define MPU_ATTR_XN		BIT(12)
+#define MPU_ATTR_XN BIT(12)
 
 /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
-#define MPU_ATTR_NO_NO (0 << 8)  /* previleged no access, unprev no access */
-#define MPU_ATTR_RW_NO (1 << 8)  /* previleged ReadWrite, unprev no access */
-#define MPU_ATTR_RW_RO (2 << 8)  /* previleged ReadWrite, unprev Read-only */
-#define MPU_ATTR_RW_RW (3 << 8)  /* previleged ReadWrite, unprev ReadWrite */
-#define MPU_ATTR_RO_NO (5 << 8)  /* previleged Read-only, unprev no access */
+#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */
+#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */
+#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */
+#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */
+#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */
 
 /* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
  * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
 #ifndef MPU_ATTR_INTERNAL_SRAM
-#define MPU_ATTR_INTERNAL_SRAM  6  /* for Internal SRAM */
+#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */
 #endif
 #ifndef MPU_ATTR_FLASH_MEMORY
-#define MPU_ATTR_FLASH_MEMORY   2  /* for flash memory */
+#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */
 #endif
 
 /* Represent RW with at most 2 MPU regions. */
diff --git a/core/cortex-m/include/mpu_private.h b/core/cortex-m/include/mpu_private.h
index e6030114c2..eca474e14d 100644
--- a/core/cortex-m/include/mpu_private.h
+++ b/core/cortex-m/include/mpu_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S
index 9d4815ac79..5cde406a58 100644
--- a/core/cortex-m/init.S
+++ b/core/cortex-m/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h
index dceda73958..eb23de7049 100644
--- a/core/cortex-m/irq_handler.h
+++ b/core/cortex-m/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,20 +23,20 @@
  * ensure it is enabled in the interrupt controller with the right priority.
  */
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void IRQ_HANDLER(irq)(void);				\
-	typedef struct {					\
-		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];	\
-	} irq_num_check_##irq;					\
-	static void __keep routine(void);			\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		TASK_START_IRQ_HANDLER(ret);			\
-		routine();					\
-		task_resched_if_needed(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	void IRQ_HANDLER(irq)(void);                                 \
+	typedef struct {                                             \
+		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];          \
+	} irq_num_check_##irq;                                       \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		TASK_START_IRQ_HANDLER(ret);                         \
+		routine();                                           \
+		task_resched_if_needed(ret);                         \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m/llsr.c b/core/cortex-m/llsr.c
index 616b8653db..0ab920f628 100644
--- a/core/cortex-m/llsr.c
+++ b/core/cortex-m/llsr.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,7 @@ uint64_t __keep __aeabi_llsr(uint64_t v, uint32_t shift)
 
 #ifdef CONFIG_LLSR_TEST
 
-static int command_llsr(int argc, char **argv)
+static int command_llsr(int argc, const char **argv)
 {
 	/* Volatile to prevent compilier optimization from interfering. */
 	volatile uint64_t start = 0x123456789ABCDEF0ull;
@@ -38,13 +38,11 @@ static int command_llsr(int argc, char **argv)
 	const struct {
 		uint32_t shift_by;
 		uint64_t result;
-	} cases[] = {
-		{0, start},
-		{16, 0x123456789ABCull},
-		{32, 0x12345678u},
-		{48, 0x1234u},
-		{64, 0u}
-	};
+	} cases[] = { { 0, start },
+		      { 16, 0x123456789ABCull },
+		      { 32, 0x12345678u },
+		      { 48, 0x1234u },
+		      { 64, 0u } };
 
 	for (x = 0; x < ARRAY_SIZE(cases); ++x) {
 		if ((start >> cases[x].shift_by) != cases[x].result) {
@@ -58,8 +56,7 @@ static int command_llsr(int argc, char **argv)
 }
 
 DECLARE_CONSOLE_COMMAND(
-		llsrtest, command_llsr,
-		"",
-		"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
+	llsrtest, command_llsr, "",
+	"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
 
-#endif  /* CONFIG_LLSR_TEST */
+#endif /* CONFIG_LLSR_TEST */
diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
index 29da931a28..c0793180dc 100644
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MPU module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "mpu.h"
 #include "console.h"
 #include "cpu.h"
@@ -37,7 +38,6 @@ bool mpu_is_unified(void)
 	return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0;
 }
 
-
 /**
  * Update a memory region.
  *
@@ -74,7 +74,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 	asm volatile("isb; dsb;");
 
 	MPU_NUMBER = region;
-	MPU_SIZE &= ~1;					/* Disable */
+	MPU_SIZE &= ~1; /* Disable */
 	if (enable) {
 		MPU_BASE = addr;
 		/*
@@ -85,8 +85,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 		 * according to the doc, but they don't ..., do a single 32-bit
 		 * one.
 		 */
-		REG32(&MPU_SIZE) = ((uint32_t)attr << 16)
-				 | (srd << 8) | ((size_bit - 1) << 1) | 1;
+		REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) |
+				   ((size_bit - 1) << 1) | 1;
 	}
 
 	asm volatile("isb; dsb;");
@@ -117,7 +117,7 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
 	 * regions must be naturally aligned to their size.
 	 */
 	uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr),
-				     alignment_log2(size));
+					alignment_log2(size));
 	uint8_t subregion_disable = 0;
 
 	if (natural_alignment >= 5) {
@@ -159,10 +159,9 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
 		*consumed = 1 << natural_alignment;
 	}
 
-	return mpu_update_region(region,
-			       addr & ~((1 << natural_alignment) - 1),
-			       natural_alignment,
-			       attr, enable, subregion_disable);
+	return mpu_update_region(region, addr & ~((1 << natural_alignment) - 1),
+				 natural_alignment, attr, enable,
+				 subregion_disable);
 }
 
 /**
@@ -188,8 +187,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 	if (size == 0)
 		return EC_SUCCESS;
 
-	rv = mpu_config_region_greedy(region, addr, size,
-				      attr, enable, &consumed);
+	rv = mpu_config_region_greedy(region, addr, size, attr, enable,
+				      &consumed);
 	if (rv != EC_SUCCESS)
 		return rv;
 	ASSERT(consumed <= size);
@@ -198,8 +197,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 
 	/* Regions other than DATA_RAM_TEXT may use two MPU regions */
 	if (size > 0 && region != REGION_DATA_RAM_TEXT) {
-		rv = mpu_config_region_greedy(region + 1, addr, size,
-					      attr, enable, &consumed);
+		rv = mpu_config_region_greedy(region + 1, addr, size, attr,
+					      enable, &consumed);
 		if (rv != EC_SUCCESS)
 			return rv;
 		ASSERT(consumed <= size);
@@ -223,8 +222,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size,
 			     uint8_t texscb)
 {
-	return mpu_config_region(region, addr, size,
-				 MPU_ATTR_RW_RW | texscb, 1);
+	return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb,
+				 1);
 }
 
 void mpu_enable(void)
@@ -247,13 +246,9 @@ int mpu_protect_data_ram(void)
 	int ret;
 
 	/* Prevent code execution from data RAM */
-	ret = mpu_config_region(REGION_DATA_RAM,
-				CONFIG_RAM_BASE,
-				CONFIG_DATA_RAM_SIZE,
-				MPU_ATTR_XN |
-				MPU_ATTR_RW_RW |
-				MPU_ATTR_INTERNAL_SRAM,
-				1);
+	ret = mpu_config_region(
+		REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -271,18 +266,16 @@ int mpu_protect_code_ram(void)
 	return mpu_config_region(REGION_STORAGE,
 				 CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF,
 				 CONFIG_CODE_RAM_SIZE,
-				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM,
-				 1);
+				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1);
 }
 #else
 int mpu_lock_ro_flash(void)
 {
 	/* Prevent execution from internal mapped RO flash */
-	return mpu_config_region(REGION_STORAGE,
-				 CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
-				 CONFIG_RO_SIZE,
-				 MPU_ATTR_XN | MPU_ATTR_RW_RW |
-				 MPU_ATTR_FLASH_MEMORY, 1);
+	return mpu_config_region(
+		REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
+		CONFIG_RO_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1);
 }
 
 /* Represent RW with at most 2 MPU regions. */
@@ -298,8 +291,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void)
 	 * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the
 	 * address used for an MPU region must be aligned to the size.
 	 */
-	aligned_size_bit =
-		__fls(regions.addr[0] & -regions.addr[0]);
+	aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]);
 	regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE);
 	regions.addr[1] = regions.addr[0] + regions.size[0];
 	regions.size[1] = CONFIG_RW_SIZE - regions.size[0];
@@ -386,10 +378,10 @@ int mpu_lock_rollback(int lock)
 
 #ifdef CONFIG_CHIP_UNCACHED_REGION
 /* Store temporarily the regions ranges to use them for the MPU configuration */
-#define REGION(_name, _flag, _start, _size) \
-	static const uint32_t CONCAT2(_region_start_, _name) \
+#define REGION(_name, _flag, _start, _size)                           \
+	static const uint32_t CONCAT2(_region_start_, _name)          \
 		__attribute__((unused, section(".unused"))) = _start; \
-	static const uint32_t CONCAT2(_region_size_, _name) \
+	static const uint32_t CONCAT2(_region_size_, _name)           \
 		__attribute__((unused, section(".unused"))) = _size;
 #include "memory_regions.inc"
 #undef REGION
@@ -424,7 +416,7 @@ int mpu_pre_init(void)
 		 * to the region size.
 		 */
 		rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN,
-			0, 0, 0);
+				       0, 0, 0);
 		if (rv != EC_SUCCESS)
 			return rv;
 	}
diff --git a/core/cortex-m/panic-internal.h b/core/cortex-m/panic-internal.h
index 1a58afa8a2..6fa6440006 100644
--- a/core/cortex-m/panic-internal.h
+++ b/core/cortex-m/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 
 void exception_panic(void) __attribute__((naked));
 
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c
index 2f71080392..3a59fcf201 100644
--- a/core/cortex-m/panic.c
+++ b/core/cortex-m/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,9 +20,8 @@
 /* Whether bus fault is ignored */
 static int bus_fault_ignored;
 
-
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
 static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7;
@@ -77,7 +76,7 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 /* Names for each of the bits in the cfs register, starting at bit 0 */
-static const char * const cfsr_name[32] = {
+static const char *const cfsr_name[32] = {
 	/* MMFSR */
 	[0] = "Instruction access violation",
 	[1] = "Data access violation",
@@ -101,11 +100,9 @@ static const char * const cfsr_name[32] = {
 };
 
 /* Names for the first 5 bits in the DFSR */
-static const char * const dfsr_name[] = {
-	"Halt request",
-	"Breakpoint",
-	"Data watchpoint/trace",
-	"Vector catch",
+static const char *const dfsr_name[] = {
+	"Halt request",		  "Breakpoint",
+	"Data watchpoint/trace",  "Vector catch",
 	"External debug request",
 };
 
@@ -281,7 +278,7 @@ void panic_data_print(const struct panic_data *pdata)
 	print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
 	print_reg(13, lregs,
 		  in_handler ? CORTEX_PANIC_REGISTER_MSP :
-				     CORTEX_PANIC_REGISTER_PSP);
+			       CORTEX_PANIC_REGISTER_PSP);
 	print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
 	print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
 
@@ -310,24 +307,23 @@ void __keep report_panic(void)
 	sp = is_frame_in_handler_stack(
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
-			   pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
 	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
+	if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
 	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
 		const uint32_t *sregs = (const uint32_t *)sp;
 		int i;
 
 		/* Skip r0-r3 and r12 registers if necessary */
 		for (i = CORTEX_PANIC_FRAME_REGISTER_R0;
-		    i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++)
+		     i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++)
 			if (IS_ENABLED(CONFIG_PANIC_STRIP_GPR))
 				pdata->cm.frame[i] = 0;
 			else
 				pdata->cm.frame[i] = sregs[i];
 
 		for (i = CORTEX_PANIC_FRAME_REGISTER_LR;
-		    i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++)
+		     i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++)
 			pdata->cm.frame[i] = sregs[i];
 
 		pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID;
@@ -401,38 +397,41 @@ void exception_panic(void)
 #endif
 		"stmia %[pregs], {r1-r11, lr}\n"
 		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6",
-		/* clang warns that we're clobbering a reserved register:
-		 * inline asm clobber list contains reserved registers: R7
-		 * [-Werror,-Winline-asm]. The intent of the clobber list is
-		 * to force pregs and pstack to be in R0 and R12, which
-		 * still holds.
-		 */
+		"bl report_panic\n"
+		:
+		: [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr)
+		:
+		/* Constraints protecting these from being clobbered.
+		 * Gcc should be using r0 & r12 for pregs and pstack. */
+		"r1", "r2", "r3", "r4", "r5", "r6",
+	/* clang warns that we're clobbering a reserved register:
+	 * inline asm clobber list contains reserved registers: R7
+	 * [-Werror,-Winline-asm]. The intent of the clobber list is
+	 * to force pregs and pstack to be in R0 and R12, which
+	 * still holds.
+	 */
 #ifndef __clang__
-			"r7",
+		"r7",
 #endif
-			"r8", "r9", "r10", "r11", "cc", "memory"
-		);
+		"r8", "r9", "r10", "r11", "cc", "memory");
 }
 
 #ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
+	__asm__("mov " STRINGIFY(
+			SOFTWARE_PANIC_INFO_REG) ", %0\n"
+						 "mov " STRINGIFY(
+							 SOFTWARE_PANIC_REASON_REG) ", %1\n"
+										    "bl exception_panic\n"
+		:
+		: "r"(info), "r"(reason));
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t *lregs;
 
 	lregs = pdata->cm.regs;
@@ -452,7 +451,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *lregs;
 
 	if (pdata && pdata->struct_version == 2) {
diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S
index 6573e0ecaa..512b48036f 100644
--- a/core/cortex-m/switch.S
+++ b/core/cortex-m/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index 2ec1ec1dc2..ce6c8c9615 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,11 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
+#include "debug.h"
 #include "link_defs.h"
 #include "panic.h"
 #include "task.h"
@@ -21,10 +23,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		atomic_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -40,12 +42,10 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -55,12 +55,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern void __switchto(task_ *from, task_ *to);
@@ -91,21 +91,20 @@ void __idle(void)
 		 * shortly therefore, resumes execution on exiting idle mode.
 		 * Workaround: Replace the idle function with the followings
 		 */
-		asm (
-			"cpsid i\n"             /* Disable interrupt */
-			"push {r0-r5}\n"        /* Save needed registers */
-			"wfi\n"                 /* Wait for int to enter idle */
-			"ldm %0, {r0-r5}\n"     /* Add a delay after WFI */
-			"pop {r0-r5}\n" /* Restore regs before enabling ints */
-			"isb\n"                 /* Flush the cpu pipeline */
-			"cpsie i\n" :: "r" (0x100A8000)  /* Enable interrupts */
+		asm("cpsid i\n" /* Disable interrupt */
+		    "push {r0-r5}\n" /* Save needed registers */
+		    "wfi\n" /* Wait for int to enter idle */
+		    "ldm %0, {r0-r5}\n" /* Add a delay after WFI */
+		    "pop {r0-r5}\n" /* Restore regs before enabling ints */
+		    "isb\n" /* Flush the cpu pipeline */
+		    "cpsie i\n" ::"r"(0x100A8000) /* Enable interrupts */
 		);
 #else
 		/*
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
 		 */
-		asm("wfi");
+		cpu_enter_suspend_mode();
 #endif
 	}
 }
@@ -121,20 +120,19 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 } tasks_init[] = {
 	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+		CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -142,17 +140,16 @@ static const struct {
 static task_ tasks[TASK_ID_COUNT];
 
 /* Reset constants and state for all tasks */
-#define TASK_RESET_SUPPORTED		BIT(31)
-#define TASK_RESET_LOCK			BIT(30)
-#define TASK_RESET_STATE_MASK		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_WAITERS_MASK		~TASK_RESET_STATE_MASK
-#define TASK_RESET_UNSUPPORTED		0
-#define TASK_RESET_STATE_LOCKED		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_STATE_UNLOCKED	TASK_RESET_SUPPORTED
+#define TASK_RESET_SUPPORTED BIT(31)
+#define TASK_RESET_LOCK BIT(30)
+#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
+#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK
+#define TASK_RESET_UNSUPPORTED 0
+#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
+#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED
 
 #ifdef CONFIG_TASK_RESET_LIST
-#define ENABLE_RESET(n) \
-	[TASK_ID_##n] = TASK_RESET_SUPPORTED,
+#define ENABLE_RESET(n) [TASK_ID_##n] = TASK_RESET_SUPPORTED,
 static uint32_t task_reset_state[TASK_ID_COUNT] = {
 #ifdef CONFIG_TASK_RESET_LIST
 	CONFIG_TASK_RESET_LIST
@@ -167,13 +164,10 @@ BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 BUILD_ASSERT(BIT(TASK_ID_COUNT) < TASK_RESET_LOCK);
 
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+				    CONFIG_CTS_TASK_LIST] __aligned(8);
 
 #undef TASK
 
@@ -210,7 +204,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -232,7 +226,7 @@ inline bool is_interrupt_enabled(void)
 	int primask;
 
 	/* Interrupts are enabled when PRIMASK bit is 0 */
-	asm("mrs %0, primask":"=r"(primask));
+	asm("mrs %0, primask" : "=r"(primask));
 
 	return !(primask & 0x1);
 }
@@ -240,8 +234,9 @@ inline bool is_interrupt_enabled(void)
 inline bool in_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr \n"             /* read exception number */
-	    "lsl %0, #23  \n":"=r"(ret)); /* exception bits are the 9 LSB */
+	asm("mrs %0, ipsr \n" /* read exception number */
+	    "lsl %0, #23  \n"
+	    : "=r"(ret)); /* exception bits are the 9 LSB */
 	return ret;
 }
 
@@ -249,8 +244,8 @@ inline bool in_interrupt_context(void)
 static inline int get_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr \n":"=r"(ret)); /* read exception number */
-	return ret & 0x1ff;               /* exception bits are the 9 LSB */
+	asm("mrs %0, ipsr \n" : "=r"(ret)); /* read exception number */
+	return ret & 0x1ff; /* exception bits are the 9 LSB */
 }
 #endif
 
@@ -351,7 +346,7 @@ void svc_handler(int desched, task_id_t resched)
 	if (next == current)
 		return;
 
-	/* Switch to new task */
+		/* Switch to new task */
 #ifdef CONFIG_TASK_PROFILING
 	task_switches++;
 #endif
@@ -364,7 +359,7 @@ void __schedule(int desched, int resched)
 	register int p0 asm("r0") = desched;
 	register int p1 asm("r1") = resched;
 
-	asm("svc 0"::"r"(p0),"r"(p1));
+	asm("svc 0" ::"r"(p0), "r"(p1));
 }
 
 #ifdef CONFIG_TASK_PROFILING
@@ -389,9 +384,9 @@ void __keep task_start_irq_handler(void *excep_return)
 	 * and we are not called from another exception (this must match the
 	 * logic for when we chain to svc_handler() below).
 	 */
-	if (!need_resched_or_profiling
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!need_resched_or_profiling ||
+	    (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+	     EXC_RETURN_MODE_HANDLER))
 		return;
 
 	exc_start_time = t;
@@ -404,9 +399,9 @@ void __keep task_resched_if_needed(void *excep_return)
 	 * Continue iff a rescheduling event happened or profiling is active,
 	 * and we are not called from another exception.
 	 */
-	if (!need_resched_or_profiling
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!need_resched_or_profiling ||
+	    (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+	     EXC_RETURN_MODE_HANDLER))
 		return;
 
 	svc_handler(0, 0);
@@ -570,10 +565,10 @@ static uint32_t init_task_context(task_id_t id)
 	tasks[id].sp = (uint32_t)sp;
 
 	/* Initial context on stack (see __switchto()) */
-	sp[8] = tasks_init[id].r0;          /* r0 */
-	sp[13] = (uint32_t)task_exit_trap;  /* lr */
-	sp[14] = tasks_init[id].pc;         /* pc */
-	sp[15] = 0x01000000;                /* psr */
+	sp[8] = tasks_init[id].r0; /* r0 */
+	sp[13] = (uint32_t)task_exit_trap; /* lr */
+	sp[14] = tasks_init[id].pc; /* pc */
+	sp[15] = 0x01000000; /* psr */
 
 	/* Fill unused stack; also used to detect stack overflow. */
 	for (sp = tasks[id].stack; sp < (uint32_t *)tasks[id].sp; sp++)
@@ -618,8 +613,7 @@ DECLARE_DEFERRED(deferred_task_reset);
  * and if it matches if_value, updates the state to new_value, and returns
  * TRUE.
  */
-static int update_reset_state(uint32_t *state,
-			      uint32_t if_value,
+static int update_reset_state(uint32_t *state, uint32_t if_value,
 			      uint32_t to_value)
 {
 	int update;
@@ -675,8 +669,7 @@ void task_enable_resets(void)
 	uint32_t *state = &task_reset_state[id];
 
 	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id: %d",
+		cprints(CC_TASK, "%s called from non-resettable task, id: %d",
 			__func__, id);
 		return;
 	}
@@ -719,8 +712,7 @@ void task_disable_resets(void)
 	uint32_t *state = &task_reset_state[id];
 
 	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id %d",
+		cprints(CC_TASK, "%s called from non-resettable task, id %d",
 			__func__, id);
 		return;
 	}
@@ -775,8 +767,8 @@ int task_reset_cleanup(void)
 	if (cleanup_req) {
 		while (!try_release_reset_lock(state)) {
 			/* Find the first waiter to notify. */
-			task_id_t notify_id = __fls(
-			    *state & TASK_RESET_WAITERS_MASK);
+			task_id_t notify_id =
+				__fls(*state & TASK_RESET_WAITERS_MASK);
 			/*
 			 * Remove the task from waiters first, so that
 			 * when it wakes after being notified, it is in
@@ -912,8 +904,9 @@ void mutex_lock(struct mutex *mtx)
 				     "   teq     %0, #0\n"
 				     "   it eq\n"
 				     "   strexeq %0, %2, [%1]\n"
-				     : "=&r" (value)
-				     : "r" (&mtx->lock), "r" (2) : "cc");
+				     : "=&r"(value)
+				     : "r"(&mtx->lock), "r"(2)
+				     : "cc");
 		/*
 		 * "value" is equals to 1 if the store conditional failed,
 		 * 2 if somebody else owns the mutex, 0 else.
@@ -976,7 +969,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -1005,12 +998,11 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL,
 			     "Print task info");
 
 #ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -1022,8 +1014,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -1078,7 +1069,7 @@ int task_start(void)
 }
 
 #ifdef CONFIG_CMD_TASK_RESET
-static int command_task_reset(int argc, char **argv)
+static int command_task_reset(int argc, const char **argv)
 {
 	task_id_t id;
 	char *e;
@@ -1093,7 +1084,6 @@ static int command_task_reset(int argc, char **argv)
 
 	return EC_ERROR_PARAM_COUNT;
 }
-DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset,
-			"task_id",
+DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, "task_id",
 			"Reset a task");
-#endif  /* CONFIG_CMD_TASK_RESET */
+#endif /* CONFIG_CMD_TASK_RESET */
diff --git a/core/cortex-m/toolchain.mk b/core/cortex-m/toolchain.mk
new file mode 100644
index 0000000000..55ca2d74cd
--- /dev/null
+++ b/core/cortex-m/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi-
+endif
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_arm),\
+	$(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c
index 4897376c1b..433898c00a 100644
--- a/core/cortex-m/vecttable.c
+++ b/core/cortex-m/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,20 +20,18 @@ typedef void (*func)(void);
 #if PASS == 1
 /* Default exception handler */
 void __attribute__((used, naked)) default_handler(void);
-void default_handler()
+void default_handler(void)
 {
-	asm(
-	".thumb_func\n"
-	"	b exception_panic"
-	);
+	asm(".thumb_func\n"
+	    "	b exception_panic");
 }
 
 #define table(x) x
 
-#define weak_with_default __attribute__((used,weak,alias("default_handler")))
+#define weak_with_default __attribute__((used, weak, alias("default_handler")))
 
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
 
 #define item(name) extern void name(void);
 #define null
@@ -59,21 +57,19 @@ void weak_with_default svc_handler(int desched, task_id_t resched);
  * This approach differs slightly from the one in the document,
  * it only loads r0 (desched) and r1 (resched) for svc_handler.
  */
-void __attribute__((used,naked)) svc_helper_handler(void);
-void svc_helper_handler()
+void __attribute__((used, naked)) svc_helper_handler(void);
+void svc_helper_handler(void)
 {
-	asm(
-	".thumb_func\n"
-	"	tst lr, #4		/* see if called from supervisor mode */\n"
-	"	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
-	"	it ne\n"
-	"	mrsne r2, psp\n"
-	"	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
-	"	ldr r0, [r2]\n"
-	"	b %0			/* call svc_handler */\n"
-	:
-	: "i"(svc_handler)
-	);
+	asm(".thumb_func\n"
+	    "	tst lr, #4		/* see if called from supervisor mode */\n"
+	    "	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
+	    "	it ne\n"
+	    "	mrsne r2, psp\n"
+	    "	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
+	    "	ldr r0, [r2]\n"
+	    "	b %0			/* call svc_handler */\n"
+	    :
+	    : "i"(svc_handler));
 }
 
 #endif /* PASS 1 */
@@ -100,277 +96,64 @@ void svc_helper_handler()
 #pragma clang diagnostic ignored "-Winitializer-overrides"
 #endif /* __clang__ */
 
-#define table(x)								\
-	const func vectors[] __attribute__((section(".text.vecttable"))) = {	\
-		x								\
-		[IRQ_UNUSED_OFFSET] = null					\
-	};
+#define table(x)                                     \
+	const func vectors[] __attribute__((section( \
+		".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null };
 
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num)                                                          \
+	[num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+		vec(irq_##num)
 
 #define item(name) name,
-#define null (void*)0,
+#define null (void *)0,
 #endif /* PASS 2 */
 
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	item(svc_helper_handler)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-	irq(32)
-	irq(33)
-	irq(34)
-	irq(35)
-	irq(36)
-	irq(37)
-	irq(38)
-	irq(39)
-	irq(40)
-	irq(41)
-	irq(42)
-	irq(43)
-	irq(44)
-	irq(45)
-	irq(46)
-	irq(47)
-	irq(48)
-	irq(49)
-	irq(50)
-	irq(51)
-	irq(52)
-	irq(53)
-	irq(54)
-	irq(55)
-	irq(56)
-	irq(57)
-	irq(58)
-	irq(59)
-	irq(60)
-	irq(61)
-	irq(62)
-	irq(63)
-	irq(64)
-	irq(65)
-	irq(66)
-	irq(67)
-	irq(68)
-	irq(69)
-	irq(70)
-	irq(71)
-	irq(72)
-	irq(73)
-	irq(74)
-	irq(75)
-	irq(76)
-	irq(77)
-	irq(78)
-	irq(79)
-	irq(80)
-	irq(81)
-	irq(82)
-	irq(83)
-	irq(84)
-	irq(85)
-	irq(86)
-	irq(87)
-	irq(88)
-	irq(89)
-	irq(90)
-	irq(91)
-	irq(92)
-	irq(93)
-	irq(94)
-	irq(95)
-	irq(96)
-	irq(97)
-	irq(98)
-	irq(99)
-	irq(100)
-	irq(101)
-	irq(102)
-	irq(103)
-	irq(104)
-	irq(105)
-	irq(106)
-	irq(107)
-	irq(108)
-	irq(109)
-	irq(110)
-	irq(111)
-	irq(112)
-	irq(113)
-	irq(114)
-	irq(115)
-	irq(116)
-	irq(117)
-	irq(118)
-	irq(119)
-	irq(120)
-	irq(121)
-	irq(122)
-	irq(123)
-	irq(124)
-	irq(125)
-	irq(126)
-	irq(127)
-	irq(128)
-	irq(129)
-	irq(130)
-	irq(131)
-	irq(132)
-	irq(133)
-	irq(134)
-	irq(135)
-	irq(136)
-	irq(137)
-	irq(138)
-	irq(139)
-	irq(140)
-	irq(141)
-	irq(142)
-	irq(143)
-	irq(144)
-	irq(145)
-	irq(146)
-	irq(147)
-	irq(148)
-	irq(149)
-	irq(150)
-	irq(151)
-	irq(152)
-	irq(153)
-	irq(154)
-	irq(155)
-	irq(156)
-	irq(157)
-	irq(158)
-	irq(159)
-	irq(160)
-	irq(161)
-	irq(162)
-	irq(163)
-	irq(164)
-	irq(165)
-	irq(166)
-	irq(167)
-	irq(168)
-	irq(169)
-	irq(170)
-	irq(171)
-	irq(172)
-	irq(173)
-	irq(174)
-	irq(175)
-	irq(176)
-	irq(177)
-	irq(178)
-	irq(179)
-	irq(180)
-	irq(181)
-	irq(182)
-	irq(183)
-	irq(184)
-	irq(185)
-	irq(186)
-	irq(187)
-	irq(188)
-	irq(189)
-	irq(190)
-	irq(191)
-	irq(192)
-	irq(193)
-	irq(194)
-	irq(195)
-	irq(196)
-	irq(197)
-	irq(198)
-	irq(199)
-	irq(200)
-	irq(201)
-	irq(202)
-	irq(203)
-	irq(204)
-	irq(205)
-	irq(206)
-	irq(207)
-	irq(208)
-	irq(209)
-	irq(210)
-	irq(211)
-	irq(212)
-	irq(213)
-	irq(214)
-	irq(215)
-	irq(216)
-	irq(217)
-	irq(218)
-	irq(219)
-	irq(220)
-	irq(221)
-	irq(222)
-	irq(223)
-	irq(224)
-	irq(225)
-	irq(226)
-	irq(227)
-	irq(228)
-	irq(229)
-	irq(230)
-	irq(231)
-	irq(232)
-	irq(233)
-	irq(234)
-	irq(235)
-	irq(236)
-	irq(237)
-	irq(238)
-	irq(239)
-)
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+	bus_fault) vec(usage_fault) null null null null item(svc_helper_handler) vec(debug)
+	      null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4) irq(
+		      5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12) irq(13)
+		      irq(14) irq(15) irq(16) irq(17) irq(18) irq(19) irq(20) irq(
+			      21) irq(22) irq(23) irq(24) irq(25) irq(26) irq(27)
+			      irq(28) irq(29) irq(30) irq(31) irq(32) irq(33) irq(
+				      34) irq(35) irq(36) irq(37) irq(38) irq(39)
+				      irq(40) irq(41) irq(42) irq(43) irq(44) irq(
+					      45) irq(46) irq(47) irq(48) irq(49)
+					      irq(50) irq(51) irq(52) irq(53) irq(
+						      54) irq(55) irq(56) irq(57)
+						      irq(58) irq(59) irq(60) irq(
+							      61) irq(62) irq(63)
+							      irq(64) irq(65) irq(
+								      66) irq(67)
+								      irq(68) irq(
+									      69) irq(70)
+									      irq(71) irq(72) irq(73) irq(74) irq(75) irq(76) irq(77) irq(78) irq(79) irq(80) irq(81) irq(82) irq(83) irq(84) irq(85) irq(86) irq(87) irq(88) irq(89) irq(90) irq(91) irq(92) irq(93) irq(94) irq(95) irq(96) irq(97) irq(
+										      98) irq(99)
+										      irq(100) irq(101) irq(102) irq(103) irq(104) irq(105) irq(106) irq(
+											      107) irq(108) irq(109) irq(110) irq(111) irq(112) irq(113) irq(114) irq(115)
+											      irq(116) irq(117) irq(118) irq(119) irq(120) irq(121) irq(122) irq(
+												      123) irq(124) irq(125) irq(126) irq(127) irq(128) irq(129) irq(130) irq(131)
+												      irq(132) irq(133) irq(134) irq(135) irq(136) irq(137) irq(138) irq(
+													      139) irq(140) irq(141) irq(142) irq(143) irq(144) irq(145) irq(146) irq(147)
+													      irq(148) irq(149) irq(150) irq(151) irq(152) irq(153) irq(154) irq(
+														      155) irq(156) irq(157) irq(158) irq(159) irq(160) irq(161) irq(162) irq(163)
+														      irq(164) irq(165) irq(166) irq(167) irq(168) irq(169) irq(170) irq(
+															      171) irq(172) irq(173) irq(174) irq(175) irq(176) irq(177) irq(178)
+															      irq(179) irq(180) irq(181) irq(182) irq(183) irq(184) irq(185) irq(
+																      186) irq(187) irq(188) irq(189) irq(190) irq(191) irq(192)
+																      irq(193) irq(194) irq(195) irq(196) irq(197) irq(198) irq(
+																	      199) irq(200) irq(201) irq(202) irq(203) irq(204)
+																	      irq(205) irq(206) irq(207) irq(208) irq(209) irq(
+																		      210) irq(211) irq(212) irq(213) irq(214)
+																		      irq(215) irq(216) irq(217) irq(218) irq(
+																			      219) irq(220) irq(221) irq(222)
+																			      irq(223) irq(224) irq(225) irq(
+																				      226) irq(227) irq(228)
+																				      irq(229) irq(230) irq(231) irq(
+																					      232) irq(233) irq(234)
+																					      irq(235) irq(236) irq(
+																						      237) irq(238)
+																						      irq(239))
 
 #if PASS == 2
 #ifdef __clang__
diff --git a/core/cortex-m/watchdog.c b/core/cortex-m/watchdog.c
index c9faf54b2b..a94c6a9c25 100644
--- a/core/cortex-m/watchdog.c
+++ b/core/cortex-m/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/__builtin.c b/core/cortex-m0/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/cortex-m0/__builtin.c
+++ b/core/cortex-m0/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h
index 7ec856ed62..9fd3ab849b 100644
--- a/core/cortex-m0/atomic.h
+++ b/core/cortex-m0/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,22 +16,22 @@
  *
  * There is no load/store exclusive on ARMv6-M, just disable interrupts
  */
-#define ATOMIC_OP(asm_op, a, v)					\
-({								\
-	uint32_t reg0, reg1;					\
-								\
-	__asm__ __volatile__(".syntax unified\n"		\
-			     "   cpsid i\n"			\
-			     "   ldr  %0, [%2]\n"		\
-			     "   mov  %1, %0\n"			\
-			     #asm_op" %0, %0, %3\n"		\
-			     "   str  %0, [%2]\n"		\
-			     "   cpsie i\n"			\
-			     : "=&l"(reg0), "=&l"(reg1)		\
-			     : "l"(a), "r"(v)			\
-			     : "cc", "memory");			\
-	reg1;							\
-})
+#define ATOMIC_OP(asm_op, a, v)                                 \
+	({                                                      \
+		uint32_t reg0, reg1;                            \
+                                                                \
+		__asm__ __volatile__(".syntax unified\n"        \
+				     "   cpsid i\n"             \
+				     "   ldr  %0, [%2]\n"       \
+				     "   mov  %1, %0\n" #asm_op \
+				     " %0, %0, %3\n"            \
+				     "   str  %0, [%2]\n"       \
+				     "   cpsie i\n"             \
+				     : "=&l"(reg0), "=&l"(reg1) \
+				     : "l"(a), "r"(v)           \
+				     : "cc", "memory");         \
+		reg1;                                           \
+	})
 
 static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 {
@@ -62,8 +62,8 @@ static inline atomic_val_t atomic_clear(atomic_t *addr)
 			     "   ldr     %0, [%1]\n"
 			     "   str     %2, [%1]\n"
 			     "   cpsie   i\n"
-			     : "=&l" (ret)
-			     : "l" (addr), "r" (0)
+			     : "=&l"(ret)
+			     : "l"(addr), "r"(0)
 			     : "cc", "memory");
 
 	return ret;
@@ -74,4 +74,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return ATOMIC_OP(ands, addr, bits);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk
index eab2a1eb1c..0bea9d09ab 100644
--- a/core/cortex-m0/build.mk
+++ b/core/cortex-m0/build.mk
@@ -1,23 +1,11 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Cortex-M0 core OS files build
 #
 
-ifeq ($(cc-name),gcc)
-# coreboot sdk
-CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
-else
-# llvm sdk
-CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
-endif
-
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	$(CROSS_COMPILE_ARM_DEFAULT))
-
 # CPU specific compilation flags
 CFLAGS_CPU+=-mthumb
 ifeq ($(cc-name),clang)
diff --git a/core/cortex-m0/config_core.h b/core/cortex-m0/config_core.h
index a40756fb49..e954e5e0af 100644
--- a/core/cortex-m0/config_core.h
+++ b/core/cortex-m0/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/cpu.c b/core/cortex-m0/cpu.c
index b354cc03e2..e180570863 100644
--- a/core/cortex-m0/cpu.c
+++ b/core/cortex-m0/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
index c30095fd65..568b16eedb 100644
--- a/core/cortex-m0/cpu.h
+++ b/core/cortex-m0/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,41 +10,42 @@
 
 #include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100)
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180)
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280)
-#define CPU_NVIC_ISPR(x)       CPUREG(0xe000e200)
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
+#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 
 /* System Control Block */
-#define CPU_SCB_ICSR           CPUREG(0xe000ed04)
+#define CPU_SCB_ICSR CPUREG(0xe000ed04)
 
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0U)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0U)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR2        CPUREG(0xe000ed1c)
-#define CPU_NVIC_SHCSR3        CPUREG(0xe000ed20)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
+#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
 
 #define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3)
 
 /* Bitfield values for EXC_RETURN. */
-#define EXC_RETURN_SPSEL_MASK	BIT(2)
-#define EXC_RETURN_SPSEL_MSP	0
-#define EXC_RETURN_SPSEL_PSP	BIT(2)
-#define EXC_RETURN_MODE_MASK	BIT(3)
-#define EXC_RETURN_MODE_HANDLER	0
-#define EXC_RETURN_MODE_THREAD	BIT(3)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
@@ -57,10 +58,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 3)
 		priority = 3;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(3 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(3 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index ce67760cf2..3c2076b9e4 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -189,6 +189,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -291,6 +295,12 @@ SECTIONS
 		__data_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated
 		 * RAM, so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/cortex-m0/include/fpu.h b/core/cortex-m0/include/fpu.h
index 3acec557a7..1054f388b0 100644
--- a/core/cortex-m0/include/fpu.h
+++ b/core/cortex-m0/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 #ifndef __CROS_EC_FPU_H
 #define __CROS_EC_FPU_H
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S
index 6ccb75bbe8..58316e92d6 100644
--- a/core/cortex-m0/init.S
+++ b/core/cortex-m0/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h
index 302befe7a6..f2f6a220e4 100644
--- a/core/cortex-m0/irq_handler.h
+++ b/core/cortex-m0/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,25 +20,26 @@
  */
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
 #ifdef CONFIG_TASK_PROFILING
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	static void routine(void);				\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_end_irq_handler(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	static void routine(void);                                   \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		task_start_irq_handler(ret);                         \
+		routine();                                           \
+		task_end_irq_handler(ret);                           \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
 #else /* CONFIG_TASK_PROFILING */
 /* No Profiling : connect directly the IRQ vector */
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	static void __keep routine(void);			\
-	void IRQ_HANDLER(irq)(void) __attribute__((alias(STRINGIFY(routine))));\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));          \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
 #endif /* CONFIG_TASK_PROFILING */
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m0/mula.S b/core/cortex-m0/mula.S
index 02e617c328..7bb54263b4 100644
--- a/core/cortex-m0/mula.S
+++ b/core/cortex-m0/mula.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/panic-internal.h b/core/cortex-m0/panic-internal.h
index 51c12f65b2..9f831495ff 100644
--- a/core/cortex-m0/panic-internal.h
+++ b/core/cortex-m0/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 noreturn void exception_panic(void) __attribute__((naked));
 
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c
index f1ee816c60..f20908eb7c 100644
--- a/core/cortex-m0/panic.c
+++ b/core/cortex-m0/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 /* Whether bus fault is ignored */
 static int bus_fault_ignored;
 
-
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
 static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7;
@@ -101,7 +100,7 @@ void panic_data_print(const struct panic_data *pdata)
 	print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
 	print_reg(13, lregs,
 		  in_handler ? CORTEX_PANIC_REGISTER_MSP :
-				     CORTEX_PANIC_REGISTER_PSP);
+			       CORTEX_PANIC_REGISTER_PSP);
 	print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
 	print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
 }
@@ -126,10 +125,9 @@ void __keep report_panic(void)
 	sp = is_frame_in_handler_stack(
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
-			   pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
 	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
+	if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
 	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
 		const uint32_t *sregs = (const uint32_t *)sp;
 		int i;
@@ -162,38 +160,41 @@ void exception_panic(void)
 		"mov r5, lr\n"
 		"stmia %[pregs]!, {r1-r5}\n"
 		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6",
-		/* clang warns that we're clobbering a reserved register:
-		 * inline asm clobber list contains reserved registers: R7
-		 * [-Werror,-Winline-asm]. The intent of the clobber list is
-		 * to force pregs and pstack to be in R0 and R12, which
-		 * still holds.
-		 */
+		"bl report_panic\n"
+		:
+		: [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr)
+		:
+		/* Constraints protecting these from being clobbered.
+		 * Gcc should be using r0 & r12 for pregs and pstack. */
+		"r1", "r2", "r3", "r4", "r5", "r6",
+	/* clang warns that we're clobbering a reserved register:
+	 * inline asm clobber list contains reserved registers: R7
+	 * [-Werror,-Winline-asm]. The intent of the clobber list is
+	 * to force pregs and pstack to be in R0 and R12, which
+	 * still holds.
+	 */
 #ifndef __clang__
-			"r7",
+		"r7",
 #endif
-			"r8", "r9", "r10", "r11", "cc", "memory"
-		);
+		"r8", "r9", "r10", "r11", "cc", "memory");
 }
 
 #ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
+	__asm__("mov " STRINGIFY(
+			SOFTWARE_PANIC_INFO_REG) ", %0\n"
+						 "mov " STRINGIFY(
+							 SOFTWARE_PANIC_REASON_REG) ", %1\n"
+										    "bl exception_panic\n"
+		:
+		: "r"(info), "r"(reason));
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t *lregs;
 
 	lregs = pdata->cm.regs;
@@ -213,7 +214,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *lregs;
 
 	if (pdata && pdata->struct_version == 2) {
diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S
index a75daad939..4914788460 100644
--- a/core/cortex-m0/switch.S
+++ b/core/cortex-m0/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index 52a6921ae6..b34e920e09 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -21,10 +22,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		atomic_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -40,12 +41,10 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -55,12 +54,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(int *task_stack_ready);
@@ -74,7 +73,7 @@ void __idle(void)
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
 		 */
-		asm("wfi");
+		cpu_enter_suspend_mode();
 	}
 }
 #endif /* !CONFIG_LOW_POWER_IDLE */
@@ -89,20 +88,19 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 } tasks_init[] = {
 	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+		CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -112,15 +110,11 @@ static task_ tasks[TASK_ID_COUNT];
 BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+				    CONFIG_CTS_TASK_LIST] __aligned(8);
 
 #undef TASK
 
@@ -144,7 +138,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -166,7 +160,7 @@ inline bool is_interrupt_enabled(void)
 	int primask;
 
 	/* Interrupts are enabled when PRIMASK bit is 0 */
-	asm("mrs %0, primask":"=r"(primask));
+	asm("mrs %0, primask" : "=r"(primask));
 
 	return !(primask & 0x1);
 }
@@ -184,7 +178,7 @@ static inline int get_interrupt_context(void)
 {
 	int ret;
 	asm("mrs %0, ipsr\n" : "=r"(ret)); /* read exception number */
-	return ret & 0x1ff;                /* exception bits are the 9 LSB */
+	return ret & 0x1ff; /* exception bits are the 9 LSB */
 }
 #endif
 
@@ -211,7 +205,7 @@ int task_start_called(void)
 /**
  * Scheduling system call
  */
-task_  __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched)
+task_ __attribute__((noinline)) * __svc_handler(int desched, task_id_t resched)
 {
 	task_ *current, *next;
 #ifdef CONFIG_TASK_PROFILING
@@ -304,9 +298,8 @@ void task_start_irq_handler(void *excep_return)
 	 * Continue iff the tasks are ready and we are not called from another
 	 * exception (as the time accouting is done in the outer irq).
 	 */
-	if (!start_called
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+			      EXC_RETURN_MODE_HANDLER))
 		return;
 
 	exc_start_time = t;
@@ -324,9 +317,8 @@ void task_end_irq_handler(void *excep_return)
 	 * Continue iff the tasks are ready and we are not called from another
 	 * exception (as the time accouting is done in the outer irq).
 	 */
-	if (!start_called
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+			      EXC_RETURN_MODE_HANDLER))
 		return;
 
 	/* Track time in interrupts */
@@ -584,7 +576,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -613,12 +605,10 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
 #ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -630,8 +620,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -657,10 +646,10 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[8] = tasks_init[i].r0;           /* r0 */
-		sp[13] = (uint32_t)task_exit_trap;  /* lr */
-		sp[14] = tasks_init[i].pc;          /* pc */
-		sp[15] = 0x01000000;                /* psr */
+		sp[8] = tasks_init[i].r0; /* r0 */
+		sp[13] = (uint32_t)task_exit_trap; /* lr */
+		sp[14] = tasks_init[i].pc; /* pc */
+		sp[15] = 0x01000000; /* psr */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S
index 5628361a94..9148a33427 100644
--- a/core/cortex-m0/thumb_case.S
+++ b/core/cortex-m0/thumb_case.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/toolchain.mk b/core/cortex-m0/toolchain.mk
new file mode 100644
index 0000000000..6b5f07ccf6
--- /dev/null
+++ b/core/cortex-m0/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
+endif
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_arm),\
+	$(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m0/vecttable.c b/core/cortex-m0/vecttable.c
index 5c69f6d6c8..3871a30055 100644
--- a/core/cortex-m0/vecttable.c
+++ b/core/cortex-m0/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
 #include "config.h"
 #include "panic-internal.h"
 #include "task.h"
-#endif  /* __INIT */
+#endif /* __INIT */
 
 typedef void (*func)(void);
 
@@ -30,7 +30,7 @@ void __attribute__((naked)) default_handler(void)
 	 * restricting the relative placement of default_handler and
 	 * exception_panic.
 	 */
-	asm volatile("bx %0\n" : : "r" (exception_panic));
+	asm volatile("bx %0\n" : : "r"(exception_panic));
 }
 
 #define table(x) x
@@ -38,8 +38,8 @@ void __attribute__((naked)) default_handler(void)
 /* Note: the alias target must be defined in this translation unit */
 #define weak_with_default __attribute__((used, weak, alias("default_handler")))
 
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
 
 #define item(name) extern void name(void);
 #define null
@@ -47,12 +47,6 @@ void __attribute__((naked)) default_handler(void)
 extern void stack_end(void); /* not technically correct, it's just a pointer */
 extern void reset(void);
 
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
-#pragma GCC diagnostic pop
-
 #endif /* PASS 1 */
 
 #if PASS == 2
@@ -77,69 +71,28 @@ extern void reset(void);
 #pragma clang diagnostic ignored "-Winitializer-overrides"
 #endif /* __clang__ */
 
-#define table(x)							     \
-	const func vectors[] __attribute__((section(".text.vecttable"))) = { \
-		x							     \
-		[IRQ_UNUSED_OFFSET] = null				     \
-	}
+#define table(x)                             \
+	const func vectors[] __attribute__(( \
+		section(".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null }
 
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num)                                                          \
+	[num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+		vec(irq_##num)
 
 #define item(name) name,
 #define null (void *)0,
 #endif /* PASS 2 */
 
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	vec(svc)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-);
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+	bus_fault) vec(usage_fault) null null null null vec(svc) vec(debug)
+	      null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4)
+		      irq(5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12)
+			      irq(13) irq(14) irq(15) irq(16) irq(17) irq(18)
+				      irq(19) irq(20) irq(21) irq(22) irq(23)
+					      irq(24) irq(25) irq(26) irq(27)
+						      irq(28) irq(29) irq(30)
+							      irq(31));
 
 #if PASS == 2
 #ifdef __clang__
diff --git a/core/cortex-m0/watchdog.c b/core/cortex-m0/watchdog.c
index 9961922ee5..b4d5c086f0 100644
--- a/core/cortex-m0/watchdog.c
+++ b/core/cortex-m0/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/host/atomic.h b/core/host/atomic.h
index a8d6882d0e..0d27e1bc6f 100644
--- a/core/host/atomic.h
+++ b/core/host/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,4 +40,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 {
 	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/host/build.mk b/core/host/build.mk
index 503aa5538a..3995e7e4e4 100644
--- a/core/host/build.mk
+++ b/core/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/core/host/cpu.h b/core/host/cpu.h
index d990e06afa..f63e0b9d23 100644
--- a/core/host/cpu.h
+++ b/core/host/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-static inline void cpu_init(void) { }
+static inline void cpu_init(void)
+{
+}
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/host/disabled.c b/core/host/disabled.c
index 759c215ebd..8f05e5e1d6 100644
--- a/core/host/disabled.c
+++ b/core/host/disabled.c
@@ -1,10 +1,13 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Disabled functions */
 
-#define DISABLED(proto) proto { }
+#define DISABLED(proto) \
+	proto           \
+	{               \
+	}
 
 DISABLED(void clock_init(void));
diff --git a/core/host/host_exe.lds b/core/host/host_exe.lds
index ab8d352ecc..b4c94c12ff 100644
--- a/core/host/host_exe.lds
+++ b/core/host/host_exe.lds
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -113,6 +113,10 @@ SECTIONS {
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		*(.rodata.deferred)
 		__deferred_funcs_end = .;
diff --git a/core/host/host_task.h b/core/host/host_task.h
index 30cd2ff594..82b33f96c5 100644
--- a/core/host/host_task.h
+++ b/core/host/host_task.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,4 +34,4 @@ void task_register_interrupt(void);
  */
 pid_t getpid(void);
 
-#endif  /* __CROS_EC_HOST_TASK_H */
+#endif /* __CROS_EC_HOST_TASK_H */
diff --git a/core/host/irq_handler.h b/core/host/irq_handler.h
index 17e3df52d9..8bbf596a57 100644
--- a/core/host/irq_handler.h
+++ b/core/host/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,16 +15,16 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)                     \
-	static void __keep routine(void);			\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_resched_if_needed(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ(irq, routine, priority)                          \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		task_start_irq_handler(ret);                         \
+		routine();                                           \
+		task_resched_if_needed(ret);                         \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/host/main.c b/core/host/main.c
index ed7032eb63..1af5fa928c 100644
--- a/core/host/main.c
+++ b/core/host/main.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 const char *__prog_name;
 
@@ -85,7 +85,7 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size)
 	 * We lose the program name as LLVM fuzzer takes over main function:
 	 * make up one.
 	 */
-	static const char *name = STRINGIFY(PROJECT)".exe";
+	static const char *name = STRINGIFY(PROJECT) ".exe";
 
 	if (!initialized) {
 		__prog_name = name;
diff --git a/core/host/panic.c b/core/host/panic.c
index 7b0829989d..ed1994f82e 100644
--- a/core/host/panic.c
+++ b/core/host/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 void panic_assert_fail(const char *msg, const char *func, const char *fname,
 		       int linenum)
 {
-	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n",
-		fname, linenum, func, msg);
+	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n", fname, linenum, func,
+		msg);
 	task_dump_trace();
 
 	puts("Fail!"); /* Inform test runner */
diff --git a/core/host/stack_trace.c b/core/host/stack_trace.c
index adef66dd44..f8918b1c57 100644
--- a/core/host/stack_trace.c
+++ b/core/host/stack_trace.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,9 +44,8 @@ static void __attribute__((noinline)) _task_dump_trace_impl(int offset)
 
 	for (i = 0; i < sz - offset; ++i) {
 		fprintf(stderr, "#%-2d %s\n", i, messages[i]);
-		/* %p is correct (as opposed to %pP) since this is the host */
-		sprintf(buf, "addr2line %p -e %s",
-			trace[i + offset], __get_prog_name());
+		sprintf(buf, "addr2line %p -e %s", trace[i + offset],
+			__get_prog_name());
 		file = popen(buf, "r");
 		if (file) {
 			nb = fread(buf, 1, sizeof(buf) - 1, file);
@@ -77,8 +76,8 @@ static void __attribute__((noinline)) _task_dump_trace_dispatch(int sig)
 	} else if (in_interrupt_context()) {
 		fprintf(stderr, "Stack trace of ISR:\n");
 	} else {
-		fprintf(stderr, "Stack trace of task %d (%s):\n",
-				running, task_get_name(running));
+		fprintf(stderr, "Stack trace of task %d (%s):\n", running,
+			task_get_name(running));
 	}
 
 	if (need_dispatch) {
diff --git a/core/host/task.c b/core/host/task.c
index f8f8dfb661..3ba241198b 100644
--- a/core/host/task.c
+++ b/core/host/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -96,22 +96,18 @@ void _run_test(void *d)
 	run_test(0, NULL);
 }
 
-#define TASK(n, r, d, s) {r, d},
+#define TASK(n, r, d, s) { r, d },
 const struct task_args task_info[TASK_ID_COUNT] = {
-	{__idle, NULL},
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-	{_run_test, NULL},
+	{ __idle, NULL },
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST{ _run_test,
+								     NULL },
 };
 #undef TASK
 
 #define TASK(n, r, d, s) #n,
-static const char * const task_names[] = {
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 	"<< test runner >>",
 };
 #undef TASK
@@ -319,14 +315,13 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 	task_print_list();
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL,
 			     "Print task info");
 
 static void _wait_for_task_started(int can_sleep)
@@ -519,8 +514,8 @@ int task_start(void)
 	 */
 	pthread_mutex_lock(&interrupt_lock);
 
-	pthread_create(&interrupt_thread, NULL,
-		       _task_int_generator_start, NULL);
+	pthread_create(&interrupt_thread, NULL, _task_int_generator_start,
+		       NULL);
 
 	/*
 	 * Tell the hooks task to continue so that it can call back to enable
@@ -557,7 +552,6 @@ static void task_enable_all_tasks_callback(void)
 		pthread_mutex_unlock(&interrupt_lock);
 		pthread_cond_wait(&scheduler_cond, &run_lock);
 	}
-
 }
 
 void task_enable_all_tasks(void)
diff --git a/core/host/timer.c b/core/host/timer.c
index 3c3695cad4..66f047cd4d 100644
--- a/core/host/timer.c
+++ b/core/host/timer.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include <stdint.h>
 #include <stdio.h>
 
+#include "builtin/assert.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -90,15 +91,12 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
 
 void timer_init(void)
 {
-
 	if (!time_set) {
 		/*
 		 * Start the timer just before the 64-bit rollover to try
 		 * and catch 32-bit rollover/truncation bugs.
 		 */
-		timestamp_t ts = {
-			.val = 0xFFFFFFF0
-		};
+		timestamp_t ts = { .val = 0xFFFFFFF0 };
 
 		force_time(ts);
 	}
diff --git a/core/host/toolchain.mk b/core/host/toolchain.mk
new file mode 100644
index 0000000000..168d0e24c2
--- /dev/null
+++ b/core/host/toolchain.mk
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CROSS_COMPILE_HOST_DEFAULT:=x86_64-pc-linux-gnu-
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_host),\
+	$(CROSS_COMPILE_HOST_DEFAULT))
diff --git a/core/minute-ia/atomic.h b/core/minute-ia/atomic.h
index dbcd04b7de..e722d799c8 100644
--- a/core/minute-ia/atomic.h
+++ b/core/minute-ia/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 #include "util.h"
 
 static inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value,
-		uint32_t new_value)
+					    uint32_t new_value)
 {
 	uint32_t _old_value = old_value;
 
 	__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchgl %2, %1"
-			     : "=a" (old_value), "+m" (*var)
-			     : "r" (new_value), "0" (old_value)
+			     : "=a"(old_value), "+m"(*var)
+			     : "r"(new_value), "0"(old_value)
 			     : "memory");
 
 	return (_old_value == old_value);
@@ -65,4 +65,4 @@ static inline atomic_val_t atomic_clear(atomic_t *addr)
 	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/minute-ia/build.mk b/core/minute-ia/build.mk
index b51512c16e..cd92c5618f 100644
--- a/core/minute-ia/build.mk
+++ b/core/minute-ia/build.mk
@@ -1,15 +1,11 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Minute-IA core build
 #
 
-# Select Minute-IA bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\
-	/opt/coreboot-sdk/bin/i386-elf-)
-
 # FPU compilation flags
 CFLAGS_FPU-$(CONFIG_FPU)=
 
diff --git a/core/minute-ia/config_core.h b/core/minute-ia/config_core.h
index 47121642a4..1dce51720d 100644
--- a/core/minute-ia/config_core.h
+++ b/core/minute-ia/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,6 @@
 /*
  * Flag indicates the task uses FPU H/W
  */
-#define MIA_TASK_FLAG_USE_FPU                   0x00000001
+#define MIA_TASK_FLAG_USE_FPU 0x00000001
 
 #endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/minute-ia/cpu.c b/core/minute-ia/cpu.c
index cef39fe1ce..0157fec90b 100644
--- a/core/minute-ia/cpu.c
+++ b/core/minute-ia/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,7 +7,6 @@
 
 #include <cpu.h>
 
-
 void cpu_init(void)
 {
 	/* Nothing to do now */
diff --git a/core/minute-ia/cpu.h b/core/minute-ia/cpu.h
index 09eb50e4ca..bf5f3c5bbd 100644
--- a/core/minute-ia/cpu.h
+++ b/core/minute-ia/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,5 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-
 void cpu_init(void);
-#endif	/* __CROS_EC_CPU_H */
+#endif /* __CROS_EC_CPU_H */
diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S
index beda1dbfae..be3e0fbf2e 100644
--- a/core/minute-ia/ec.lds.S
+++ b/core/minute-ia/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -156,6 +156,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -216,6 +220,12 @@ SECTIONS
 		 __bss_end = .;
 		 __bss_size_words = ABSOLUTE((__bss_end - __bss_start) / 4);
 
+		 /*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
 		/*
 		 * Shared memory buffer must be at the end of
 		 * preallocated RAM, so it can expand to use all the
diff --git a/core/minute-ia/ia_structs.h b/core/minute-ia/ia_structs.h
index 29bbb6c005..83214e2c1b 100644
--- a/core/minute-ia/ia_structs.h
+++ b/core/minute-ia/ia_structs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,6 @@
 
 #include "common.h"
 
-
 /**
  * IA32/x86 architecture related data structure definitions.
  * including: Global Descriptor Table (GDT), Local Descriptor Table (LDT),
@@ -24,16 +23,16 @@
 struct gdt_entry {
 	union {
 		struct {
-			uint32_t dword_lo;	/* lower dword */
-			uint32_t dword_up;	/* upper dword */
+			uint32_t dword_lo; /* lower dword */
+			uint32_t dword_up; /* upper dword */
 		};
 		struct {
-			uint16_t limit_lw;	/* limit (0:15) */
-			uint16_t base_addr_lw;	/* base address (0:15) */
-			uint8_t base_addr_mb;	/* base address (16:23) */
-			uint8_t flags;		/* flags */
-			uint8_t limit_ub;	/* limit (16:19) */
-			uint8_t base_addr_ub;	/* base address (24:31) */
+			uint16_t limit_lw; /* limit (0:15) */
+			uint16_t base_addr_lw; /* base address (0:15) */
+			uint8_t base_addr_mb; /* base address (16:23) */
+			uint8_t flags; /* flags */
+			uint8_t limit_ub; /* limit (16:19) */
+			uint8_t base_addr_ub; /* base address (24:31) */
 		};
 	};
 
@@ -43,32 +42,32 @@ typedef struct gdt_entry ldt_entry;
 
 /* GDT header */
 struct gdt_header {
-	uint16_t limit;			/* GDT limit size */
-	struct gdt_entry *entries;	/* pointer to GDT entries */
+	uint16_t limit; /* GDT limit size */
+	struct gdt_entry *entries; /* pointer to GDT entries */
 } __packed;
 
 /* IDT entry descriptor */
 struct idt_entry {
 	union {
 		struct {
-			uint32_t dword_lo;	/* lower dword */
-			uint32_t dword_up;	/* upper dword */
+			uint32_t dword_lo; /* lower dword */
+			uint32_t dword_up; /* upper dword */
 		};
 
 		struct {
-			uint16_t offset_lw;	/* offset (0:15) */
-			uint16_t seg_selector;	/* segment selector */
-			uint8_t zero;		/* must be set to zero */
-			uint8_t flags;		/* flags */
-			uint16_t offset_uw;	/* offset (16:31) */
+			uint16_t offset_lw; /* offset (0:15) */
+			uint16_t seg_selector; /* segment selector */
+			uint8_t zero; /* must be set to zero */
+			uint8_t flags; /* flags */
+			uint16_t offset_uw; /* offset (16:31) */
 		};
 	};
 } __packed;
 
 /* IDT header */
 struct idt_header {
-	uint16_t limit;			/* IDT limit size */
-	struct idt_entry *entries;	/* pointer to IDT entries */
+	uint16_t limit; /* IDT limit size */
+	struct idt_entry *entries; /* pointer to IDT entries */
 } __packed;
 
 /* TSS entry descriptor */
@@ -117,22 +116,22 @@ struct tss_entry {
 #endif
 
 /* code segment flag,  E/R, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_CODE_FLAGS	(0x9B)
+#define GDT_DESC_CODE_FLAGS (0x9B)
 
 /* data segment flag,  R/W, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_DATA_FLAGS	(0x93)
+#define GDT_DESC_DATA_FLAGS (0x93)
 
 /* TSS segment limit size */
-#define GDT_DESC_TSS_LIMIT	(0x67)
+#define GDT_DESC_TSS_LIMIT (0x67)
 
 /* TSS segment flag, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_TSS_FLAGS	(0x89)
+#define GDT_DESC_TSS_FLAGS (0x89)
 
 /* LDT segment flag, Present = 1, DPL = 0 */
-#define GDT_DESC_LDT_FLAGS	(0x82)
+#define GDT_DESC_LDT_FLAGS (0x82)
 
 /* IDT descriptor flag, Present = 1, DPL = 0, 32-bit interrupt gate */
-#define IDT_DESC_FLAGS		(0x8E)
+#define IDT_DESC_FLAGS (0x8E)
 
 /**
  * macros helper to create a GDT entry descriptor
@@ -141,21 +140,20 @@ struct tss_entry {
  * limit: 32bit limit size of bytes (will covert to unit of 4096-byte pages)
  * flags: 8bit flags
  */
-#define GEN_GDT_DESC_LO(base, limit, flags)                                    \
-	((((limit) >> 12) & 0xFFFF) | (((base) & 0xFFFF) << 16))
-
-#define GEN_GDT_DESC_UP(base, limit, flags)                                    \
-	((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) |                 \
-	(((limit) >> 12) & 0xFF0000) | ((base) & 0xFF000000) | 0xc00000)
+#define GEN_GDT_DESC_LO(base, limit, flags) \
+	((((limit) >> 12) & 0xFFFF) | (((base)&0xFFFF) << 16))
 
+#define GEN_GDT_DESC_UP(base, limit, flags)                    \
+	((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) | \
+	 (((limit) >> 12) & 0xFF0000) | ((base)&0xFF000000) | 0xc00000)
 
 /**
  * macro helper to create a IDT entry descriptor
  */
-#define GEN_IDT_DESC_LO(offset, selector, flags)                               \
-	(((uint32_t)(offset) & 0xFFFF) | (((selector) & 0xFFFF) << 16))
+#define GEN_IDT_DESC_LO(offset, selector, flags) \
+	(((uint32_t)(offset)&0xFFFF) | (((selector)&0xFFFF) << 16))
 
-#define GEN_IDT_DESC_UP(offset, selector, flags)                               \
-	(((uint32_t)(offset) & 0xFFFF0000) | (((flags) & 0xFF) << 8))
+#define GEN_IDT_DESC_UP(offset, selector, flags) \
+	(((uint32_t)(offset)&0xFFFF0000) | (((flags)&0xFF) << 8))
 
 #endif /* __CROS_EC_IA_STRUCTS_H */
diff --git a/core/minute-ia/include/fpu.h b/core/minute-ia/include/fpu.h
index 553807352a..9c0e818099 100644
--- a/core/minute-ia/include/fpu.h
+++ b/core/minute-ia/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,15 @@
 
 #ifdef CONFIG_FPU
 
-#define M_PI            3.14159265358979323846
-#define M_PI_2          1.57079632679489661923
+#define M_PI 3.14159265358979323846
+#define M_PI_2 1.57079632679489661923
 
 static inline float sqrtf(float v)
 {
 	float root;
 
 	/* root = fsqart (v); */
-	asm volatile(
-		"fsqrt"
-		: "=t" (root)
-		: "0" (v)
-	);
+	asm volatile("fsqrt" : "=t"(root) : "0"(v));
 	return root;
 }
 
@@ -34,11 +30,7 @@ static inline float fabsf(float v)
 	float root;
 
 	/* root = fabs (v); */
-	asm volatile(
-		"fabs"
-		: "=t" (root)
-		: "0" (v)
-	);
+	asm volatile("fabs" : "=t"(root) : "0"(v));
 	return root;
 }
 
@@ -51,12 +43,11 @@ static inline float logf(float v)
 {
 	float res;
 
-	asm volatile(
-		"fldln2\n"
-		"fxch\n"
-		"fyl2x\n"
-		: "=t" (res)
-		: "0" (v));
+	asm volatile("fldln2\n"
+		     "fxch\n"
+		     "fyl2x\n"
+		     : "=t"(res)
+		     : "0"(v));
 
 	return res;
 }
@@ -70,20 +61,19 @@ static inline float expf(float v)
 {
 	float res;
 
-	asm volatile(
-		"fldl2e\n"
-		"fmulp\n"
-		"fld %%st(0)\n"
-		"frndint\n"
-		"fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */
-		"fxch %%st(1)\n"
-		"f2xm1\n"
-		"fld1\n"
-		"faddp\n"
-		"fscale\n"
-		"fstp %%st(1)\n"
-		: "=t" (res)
-		: "0" (v));
+	asm volatile("fldl2e\n"
+		     "fmulp\n"
+		     "fld %%st(0)\n"
+		     "frndint\n"
+		     "fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */
+		     "fxch %%st(1)\n"
+		     "f2xm1\n"
+		     "fld1\n"
+		     "faddp\n"
+		     "fscale\n"
+		     "fstp %%st(1)\n"
+		     : "=t"(res)
+		     : "0"(v));
 
 	return res;
 }
@@ -97,24 +87,23 @@ static inline float powf(float x, float y)
 {
 	float res;
 
-	asm volatile(
-		"fyl2x\n"
-		"fld %%st(0)\n"
-		"frndint\n"
-		"fsub %%st,%%st(1)\n"
-		"fxch\n"
-		"fchs\n"
-		"f2xm1\n"
-		"fld1\n"
-		"faddp\n"
-		"fxch\n"
-		"fld1\n"
-		"fscale\n"
-		"fstp %%st(1)\n"
-		"fmulp\n"
-		: "=t" (res)
-		: "0" (x), "u" (y)
-		: "st(1)");
+	asm volatile("fyl2x\n"
+		     "fld %%st(0)\n"
+		     "frndint\n"
+		     "fsub %%st,%%st(1)\n"
+		     "fxch\n"
+		     "fchs\n"
+		     "f2xm1\n"
+		     "fld1\n"
+		     "faddp\n"
+		     "fxch\n"
+		     "fld1\n"
+		     "fscale\n"
+		     "fstp %%st(1)\n"
+		     "fmulp\n"
+		     : "=t"(res)
+		     : "0"(x), "u"(y)
+		     : "st(1)");
 
 	return res;
 }
@@ -125,16 +114,15 @@ static inline float ceilf(float v)
 	float res;
 	unsigned short control_word, control_word_tmp;
 
-	asm volatile("fnstcw %0" : "=m" (control_word));
+	asm volatile("fnstcw %0" : "=m"(control_word));
 	/* Set Rounding Mode to 10B, round up toward +infinity */
 	control_word_tmp = (control_word | 0x0800) & 0xfbff;
-	asm volatile(
-		"fld %3\n"
-		"fldcw %1\n"
-		"frndint\n"
-		"fldcw %2"
-		: "=t" (res)
-		: "m" (control_word_tmp), "m"(control_word), "m" (v));
+	asm volatile("fld %3\n"
+		     "fldcw %1\n"
+		     "frndint\n"
+		     "fldcw %2"
+		     : "=t"(res)
+		     : "m"(control_word_tmp), "m"(control_word), "m"(v));
 
 	return res;
 }
@@ -144,7 +132,7 @@ static inline float atan2f(float y, float x)
 {
 	float res;
 
-	asm volatile("fpatan" : "=t" (res) : "0" (x), "u" (y) : "st(1)");
+	asm volatile("fpatan" : "=t"(res) : "0"(x), "u"(y) : "st(1)");
 
 	return res;
 }
@@ -154,11 +142,10 @@ static inline float atanf(float v)
 {
 	float res;
 
-	asm volatile(
-		"fld1\n"
-		"fpatan\n"
-		: "=t" (res)
-		: "0" (v));
+	asm volatile("fld1\n"
+		     "fpatan\n"
+		     : "=t"(res)
+		     : "0"(v));
 
 	return res;
 }
@@ -168,7 +155,7 @@ static inline float sinf(float v)
 {
 	float res;
 
-	asm volatile("fsin" : "=t" (res) : "0" (v));
+	asm volatile("fsin" : "=t"(res) : "0"(v));
 
 	return res;
 }
@@ -178,7 +165,7 @@ static inline float cosf(float v)
 {
 	float res;
 
-	asm volatile("fcos" : "=t" (res) : "0" (v));
+	asm volatile("fcos" : "=t"(res) : "0"(v));
 
 	return res;
 }
@@ -189,5 +176,5 @@ static inline float acosf(float v)
 	return atan2f(sqrtf(1.0 - v * v), v);
 }
 
-#endif  /* CONFIG_FPU */
-#endif  /* __CROS_EC_FPU_H */
+#endif /* CONFIG_FPU */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/minute-ia/init.S b/core/minute-ia/init.S
index b8e51ccc91..4d3ac47da6 100644
--- a/core/minute-ia/init.S
+++ b/core/minute-ia/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c
index 2d55d3129e..34baa68fa8 100644
--- a/core/minute-ia/interrupts.c
+++ b/core/minute-ia/interrupts.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* The IDT  - initialized in init.S */
 extern struct idt_entry __idt[NUM_VECTORS];
@@ -54,7 +54,7 @@ static void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val)
  * bitmap for current IRQ's mask status
  * ISH support max 64 IRQs, 64 bit bitmap value is ok
  */
-#define ISH_MAX_IOAPIC_IRQS	(64)
+#define ISH_MAX_IOAPIC_IRQS (64)
 uint64_t ioapic_irq_mask_bitmap;
 
 /**
@@ -70,7 +70,7 @@ uint64_t disable_all_interrupts(void)
 	uint64_t saved_map;
 	int i;
 
-	saved_map =  ioapic_irq_mask_bitmap;
+	saved_map = ioapic_irq_mask_bitmap;
 
 	for (i = 0; i < ISH_MAX_IOAPIC_IRQS; i++) {
 		if (((uint64_t)0x1 << i) & saved_map)
@@ -179,27 +179,27 @@ static const irq_desc_t system_irqs[] = {
  * and go directly to the CPU core, so get_current_interrupt_vector
  * cannot be used.
  */
-#define DEFINE_EXN_HANDLER(vector)			\
+#define DEFINE_EXN_HANDLER(vector) \
 	_DEFINE_EXN_HANDLER(vector, exception_panic_##vector)
-#define _DEFINE_EXN_HANDLER(vector, name)		\
-	void __keep name(void);				\
-	noreturn void name(void)	\
-	{						\
-		__asm__ ("push $0\n"			\
-			 "push $" #vector "\n"		\
-			 "call exception_panic\n");	\
-		__builtin_unreachable();		\
+#define _DEFINE_EXN_HANDLER(vector, name)          \
+	void __keep name(void);                    \
+	noreturn void name(void)                   \
+	{                                          \
+		__asm__("push $0\n"                \
+			"push $" #vector "\n"      \
+			"call exception_panic\n"); \
+		__builtin_unreachable();           \
 	}
 
-#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector)		\
+#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector) \
 	_DEFINE_EXN_HANDLER_W_ERRORCODE(vector, exception_panic_##vector)
-#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name)	\
-	void __keep name(void);				\
-	noreturn void name(void)	\
-	{						\
-		__asm__ ("push $" #vector "\n"		\
-			 "call exception_panic\n");	\
-		__builtin_unreachable();		\
+#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name) \
+	void __keep name(void);                       \
+	noreturn void name(void)                      \
+	{                                             \
+		__asm__("push $" #vector "\n"         \
+			"call exception_panic\n");    \
+		__builtin_unreachable();              \
 	}
 
 DEFINE_EXN_HANDLER(0);
@@ -228,15 +228,10 @@ DEFINE_EXN_HANDLER(20);
  * watchdog timer expiration. However, this time, hardware does not
  * push errorcode, and we must account for that by pushing zero.
  */
-noreturn __keep
-void exception_panic_wdt(uint32_t cs)
+noreturn __keep void exception_panic_wdt(uint32_t cs)
 {
-	exception_panic(
-		CONFIG_MIA_WDT_VEC,
-		0,
-		(uint32_t)__builtin_return_address(0),
-		cs,
-		0);
+	exception_panic(CONFIG_MIA_WDT_VEC, 0,
+			(uint32_t)__builtin_return_address(0), cs, 0);
 }
 
 void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags)
@@ -244,7 +239,7 @@ void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags)
 	uint16_t code_segment;
 
 	/* When the flat model is used the CS will never change. */
-	__asm volatile ("mov %%cs, %0":"=r" (code_segment));
+	__asm volatile("mov %%cs, %0" : "=r"(code_segment));
 
 	__idt[num].dword_lo = GEN_IDT_DESC_LO(func, code_segment, flags);
 	__idt[num].dword_up = GEN_IDT_DESC_UP(func, code_segment, flags);
@@ -384,26 +379,28 @@ void handle_lapic_lvt_error(void)
 
 /* LAPIC LVT error is not an IRQ and can not use DECLARE_IRQ() to call. */
 void _lapic_error_handler(void);
-__asm__ (
-	".section .text._lapic_error_handler\n"
+__asm__(".section .text._lapic_error_handler\n"
 	"_lapic_error_handler:\n"
-		"pusha\n"
-		ASM_LOCK_PREFIX "addl $1, __in_isr\n"
-		"movl %esp, %eax\n"
-		"movl $stack_end, %esp\n"
-		"push %eax\n"
+	"pusha\n" ASM_LOCK_PREFIX "addl $1, __in_isr\n"
+	"movl %esp, %eax\n"
+	"movl $stack_end, %esp\n"
+	"push %eax\n"
 #ifdef CONFIG_TASK_PROFILING
-		"push $" STRINGIFY(CONFIG_IRQ_COUNT) "\n"
-		"call task_start_irq_handler\n"
-		"addl $0x04, %esp\n"
+	"push $" STRINGIFY(
+		CONFIG_IRQ_COUNT) "\n"
+				  "call task_start_irq_handler\n"
+				  "addl $0x04, %esp\n"
 #endif
-		"call handle_lapic_lvt_error\n"
-		"pop %esp\n"
-		"movl $0x00, (0xFEE000B0)\n"	/* Set EOI for LAPIC */
-		ASM_LOCK_PREFIX "subl $1, __in_isr\n"
-		"popa\n"
-		"iret\n"
-	);
+				  "call handle_lapic_lvt_error\n"
+				  "pop %esp\n"
+				  "movl $0x00, (0xFEE000B0)\n" /* Set
+								  EOI
+								  for
+								  LAPIC
+								*/
+	ASM_LOCK_PREFIX "subl $1, __in_isr\n"
+				  "popa\n"
+				  "iret\n");
 
 /* Should only be called in interrupt context */
 void unhandled_vector(void)
@@ -411,7 +408,7 @@ void unhandled_vector(void)
 	uint32_t vec = get_current_interrupt_vector();
 	CPRINTF("Ignoring vector 0x%0x!\n", vec);
 	/* Put the vector number in eax so default_int_handler can use it */
-	asm("" : : "a" (vec));
+	asm("" : : "a"(vec));
 }
 
 /**
@@ -454,8 +451,7 @@ void init_interrupts(void)
 
 	/* Setup gates for IRQs declared by drivers using DECLARE_IRQ */
 	for (p = __irq_data; p < __irq_data_end; p++)
-		set_interrupt_gate(IRQ_TO_VEC(p->irq),
-				   p->handler,
+		set_interrupt_gate(IRQ_TO_VEC(p->irq), p->handler,
 				   IDT_DESC_FLAGS);
 
 	/* Software generated IRQ */
@@ -474,11 +470,11 @@ void init_interrupts(void)
 	for (entry = 0; entry < num_system_irqs; entry++)
 		set_ioapic_redtbl_raw(system_irqs[entry].irq,
 				      system_irqs[entry].vector |
-				      IOAPIC_REDTBL_DELMOD_FIXED |
-				      IOAPIC_REDTBL_DESTMOD_PHYS |
-				      IOAPIC_REDTBL_MASK |
-				      system_irqs[entry].polarity |
-				      system_irqs[entry].trigger);
+					      IOAPIC_REDTBL_DELMOD_FIXED |
+					      IOAPIC_REDTBL_DESTMOD_PHYS |
+					      IOAPIC_REDTBL_MASK |
+					      system_irqs[entry].polarity |
+					      system_irqs[entry].trigger);
 
 	set_interrupt_gate(ISH_TS_VECTOR, __switchto, IDT_DESC_FLAGS);
 
diff --git a/core/minute-ia/interrupts.h b/core/minute-ia/interrupts.h
index 3a951a5ddb..65b26c437e 100644
--- a/core/minute-ia/interrupts.h
+++ b/core/minute-ia/interrupts.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #ifndef __ASSEMBLER__
 #include <stdint.h>
 
-#define USHRT_MAX		0xFFFF
+#define USHRT_MAX 0xFFFF
 typedef struct {
 	unsigned irq;
 	unsigned trigger;
@@ -19,13 +19,11 @@ typedef struct {
 	unsigned vector;
 } irq_desc_t;
 
-#define INTR_DESC(__irq,__vector,__trig)                    \
-    {                                                       \
-        .irq            = __irq,                            \
-        .trigger        = __trig,                           \
-        .polarity       = IOAPIC_REDTBL_INTPOL_HIGH,        \
-        .vector         = __vector	                    \
-    }
+#define INTR_DESC(__irq, __vector, __trig)                                \
+	{                                                                 \
+		.irq = __irq, .trigger = __trig,                          \
+		.polarity = IOAPIC_REDTBL_INTPOL_HIGH, .vector = __vector \
+	}
 
 #define LEVEL_INTR(__irq, __vector) \
 	INTR_DESC(__irq, __vector, IOAPIC_REDTBL_TRIGGER_LEVEL)
@@ -34,18 +32,18 @@ typedef struct {
 #endif
 
 /* ISH has a single core processor */
-#define DEST_APIC_ID			0
-#define NUM_VECTORS			256
+#define DEST_APIC_ID 0
+#define NUM_VECTORS 256
 
 /* APIC bit definitions. */
-#define APIC_DIV_16			0x03
-#define APIC_ENABLE_BIT			(1UL << 8UL)
-#define APIC_SPURIOUS_INT		REG32(ISH_LAPIC_BASE + 0xF0UL )
-#define APIC_LVT_ERROR			REG32(ISH_LAPIC_BASE + 0x370UL)
+#define APIC_DIV_16 0x03
+#define APIC_ENABLE_BIT (1UL << 8UL)
+#define APIC_SPURIOUS_INT REG32(ISH_LAPIC_BASE + 0xF0UL)
+#define APIC_LVT_ERROR REG32(ISH_LAPIC_BASE + 0x370UL)
 
 #ifndef __ASSEMBLER__
 
-typedef void (*isr_handler_t) (void);
+typedef void (*isr_handler_t)(void);
 
 void init_interrupts(void);
 void mask_interrupt(unsigned int irq);
@@ -66,4 +64,4 @@ void restore_interrupts(uint64_t irq_map);
 uint32_t get_current_interrupt_vector(void);
 #endif
 
-#endif	/* __CROS_EC_IA32_INTERRUPTS_H */
+#endif /* __CROS_EC_IA32_INTERRUPTS_H */
diff --git a/core/minute-ia/irq_handler.h b/core/minute-ia/irq_handler.h
index 30106603d6..deb8048e12 100644
--- a/core/minute-ia/irq_handler.h
+++ b/core/minute-ia/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #include "task.h"
 #include "task_defs.h"
 
-asm (".include \"core/minute-ia/irq_handler_common.S\"");
+asm(".include \"core/minute-ia/irq_handler_common.S\"");
 
 /* Helper macros to build the IRQ handler and priority struct names */
 #define IRQ_HANDLER(irqname) CONCAT3(_irq_, irqname, _handler)
@@ -30,26 +30,24 @@ asm (".include \"core/minute-ia/irq_handler_common.S\"");
  * Each irq has a irq_data structure placed in .rodata.irqs section,
  * to be used for dynamically setting up interrupt gates
  */
-#define DECLARE_IRQ_(irq_, routine_, vector)				\
-	static void __keep routine_(void);				\
-	void IRQ_HANDLER(irq_)(void);					\
-	__asm__ (".section .rodata.irqs\n");				\
-	const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_)	\
-	__attribute__((section(".rodata.irqs"))) = {			\
-		.irq = irq_,						\
-		.routine = routine_,					\
-		.handler = IRQ_HANDLER(irq_)				\
-	};								\
-	__asm__ (							\
-		".section .text._irq_" #irq_ "_handler\n"		\
-		"_irq_" #irq_ "_handler:\n"				\
-		"pusha\n"						\
-		ASM_LOCK_PREFIX "addl  $1, __in_isr\n"			\
-		"irq_handler_common $0 $0 $" #irq_ "\n"			\
-		"movl $"#vector ", " STRINGIFY(IOAPIC_EOI_REG_ADDR) "\n" \
-		"movl $0x00, " STRINGIFY(LAPIC_EOI_REG_ADDR) "\n"	\
-		ASM_LOCK_PREFIX "subl  $1, __in_isr\n"			\
-		"popa\n"						\
-		"iret\n"						\
-	)
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ_(irq_, routine_, vector)                                                    \
+	static void __keep routine_(void);                                                      \
+	void IRQ_HANDLER(irq_)(void);                                                           \
+	__asm__(".section .rodata.irqs\n");                                                     \
+	const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_)                          \
+		__attribute__((section(                                                         \
+			".rodata.irqs"))) = { .irq = irq_,                                      \
+					      .routine = routine_,                              \
+					      .handler = IRQ_HANDLER(irq_) };                   \
+	__asm__(".section .text._irq_" #irq_ "_handler\n"                                       \
+		"_irq_" #irq_ "_handler:\n"                                                     \
+		"pusha\n" ASM_LOCK_PREFIX "addl  $1, __in_isr\n"                                \
+		"irq_handler_common $0 $0 $" #irq_ "\n"                                         \
+		"movl $" #vector ", " STRINGIFY(                                                \
+			IOAPIC_EOI_REG_ADDR) "\n"                                               \
+					     "movl $0x00, " STRINGIFY(                          \
+						     LAPIC_EOI_REG_ADDR) "\n" ASM_LOCK_PREFIX   \
+									 "subl  $1, __in_isr\n" \
+									 "popa\n"               \
+									 "iret\n")
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/minute-ia/irq_handler_common.S b/core/minute-ia/irq_handler_common.S
index e07cf26ce1..2445f83730 100644
--- a/core/minute-ia/irq_handler_common.S
+++ b/core/minute-ia/irq_handler_common.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/mia_panic_internal.h b/core/minute-ia/mia_panic_internal.h
index 748ccbf2dd..d9d213ca85 100644
--- a/core/minute-ia/mia_panic_internal.h
+++ b/core/minute-ia/mia_panic_internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,5 @@
  * convenientely in the same order as pushed by hardwared during a
  * processor exception.
  */
-noreturn
-void exception_panic(
-	uint32_t vector,
-	uint32_t errorcode,
-	uint32_t eip,
-	uint32_t cs,
-	uint32_t eflags);
+noreturn void exception_panic(uint32_t vector, uint32_t errorcode, uint32_t eip,
+			      uint32_t cs, uint32_t eflags);
diff --git a/core/minute-ia/mpu.c b/core/minute-ia/mpu.c
index 389668ea6f..d91d71f99c 100644
--- a/core/minute-ia/mpu.c
+++ b/core/minute-ia/mpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/minute-ia/panic.c b/core/minute-ia/panic.c
index b4299d9e17..d02778891d 100644
--- a/core/minute-ia/panic.c
+++ b/core/minute-ia/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,13 +57,12 @@ void panic_data_print(const struct panic_data *pdata)
 	else if (pdata->x86.vector <= 20)
 		panic_printf("Reason: %s\n", panic_reason[pdata->x86.vector]);
 	else if (panic_sw_reason_is_valid(pdata->x86.vector)) {
-		panic_printf("Software panic reason %s\n",
-			     panic_sw_reasons[pdata->x86.vector -
-					      PANIC_SW_BASE]);
+		panic_printf(
+			"Software panic reason %s\n",
+			panic_sw_reasons[pdata->x86.vector - PANIC_SW_BASE]);
 		panic_printf("Software panic info 0x%x\n",
 			     pdata->x86.error_code);
-	}
-	else
+	} else
 		panic_printf("Interrupt vector number: 0x%08X (unknown)\n",
 			     pdata->x86.vector);
 	panic_printf("\n");
@@ -91,12 +90,8 @@ void panic_data_print(const struct panic_data *pdata)
  * order pushed to the stack by hardware: see "Intel 64 and IA-32
  * Architectures Software Developer's Manual", Volume 3A, Figure 6-4.
  */
-void exception_panic(
-	uint32_t vector,
-	uint32_t error_code,
-	uint32_t eip,
-	uint32_t cs,
-	uint32_t eflags)
+void exception_panic(uint32_t vector, uint32_t error_code, uint32_t eip,
+		     uint32_t cs, uint32_t eflags)
 {
 	/*
 	 * If a panic were to occur during the reset procedure, we want
@@ -176,26 +171,22 @@ void exception_panic(
 	__builtin_unreachable();
 }
 
-noreturn
-void software_panic(uint32_t reason, uint32_t info)
+noreturn void software_panic(uint32_t reason, uint32_t info)
 {
 	uint16_t code_segment;
 
 	/* Get the current code segment */
-	__asm__ volatile ("movw  %%cs, %0":"=m" (code_segment));
+	__asm__ volatile("movw  %%cs, %0" : "=m"(code_segment));
 
-	exception_panic(reason,
-			info,
-			(uint32_t)__builtin_return_address(0),
-			code_segment,
-			0);
+	exception_panic(reason, info, (uint32_t)__builtin_return_address(0),
+			code_segment, 0);
 
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	/* Setup panic data structure */
 	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
@@ -212,7 +203,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 
 	if (pdata && pdata->struct_version == 2) {
 		*reason = pdata->x86.vector;
diff --git a/core/minute-ia/switch.S b/core/minute-ia/switch.S
index cec3f904f9..b014bb4c29 100644
--- a/core/minute-ia/switch.S
+++ b/core/minute-ia/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c
index 4eb33e295a..79ce82fd89 100644
--- a/core/minute-ia/task.c
+++ b/core/minute-ia/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,7 @@
 #define TEST_TASK_EXTRA_ARGS 0
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "link_defs.h"
@@ -26,8 +27,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Value to store in unused stack */
 #define STACK_UNUSED_VALUE 0xdeadd00d
@@ -43,11 +44,9 @@ CONFIG_TEST_TASK_LIST
 extern volatile uint32_t __in_isr;
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s, f)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s, f) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -57,12 +56,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static atomic_t svc_calls;	 /* Number of service calls */
-static uint32_t task_switches;	/* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];	/* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static atomic_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 void __schedule(int desched, int resched);
@@ -97,22 +96,20 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s, f)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-	.flags = f,		\
-},
+#define TASK(n, r, d, s, f)        \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+		.flags = f,        \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 	uint32_t flags;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 
 #undef TASK
 
@@ -122,18 +119,13 @@ static task_ tasks[TASK_ID_COUNT];
 BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s, f)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s, f) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
-
 task_ *current_task, *next_task;
 
 /*
@@ -151,7 +143,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -160,7 +152,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 
 void interrupt_disable(void)
 {
-	__asm__ __volatile__ ("cli");
+	__asm__ __volatile__("cli");
 }
 
 void interrupt_enable(void)
@@ -170,16 +162,16 @@ void interrupt_enable(void)
 	 */
 	ASSERT(task_start_called() != 1);
 
-	__asm__ __volatile__ ("sti");
+	__asm__ __volatile__("sti");
 }
 
 inline bool is_interrupt_enabled(void)
 {
 	uint32_t eflags = 0;
 
-	__asm__ __volatile__ ("pushfl\n"
-			      "popl %0\n"
-			      : "=r"(eflags));
+	__asm__ __volatile__("pushfl\n"
+			     "popl %0\n"
+			     : "=r"(eflags));
 
 	/* Check Interrupt Enable flag */
 	return eflags & 0x200;
@@ -251,8 +243,7 @@ uint32_t switch_handler(int desched, task_id_t resched)
 	next = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
 
 	/* Only the first ISR on the (nested IRQ) stack calculates time */
-	if (IS_ENABLED(CONFIG_TASK_PROFILING) &&
-	    __in_isr == 1) {
+	if (IS_ENABLED(CONFIG_TASK_PROFILING) && __in_isr == 1) {
 		/* Track time in interrupts */
 		uint32_t t = get_time().le.lo;
 
@@ -465,11 +456,10 @@ void mutex_lock(struct mutex *mtx)
 
 	do {
 		old_val = 0;
-		__asm__ __volatile__(
-				ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
-				: "=a" (old_val)
-				: "r" (value), "m" (mtx->lock), "a" (old_val)
-				: "memory");
+		__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
+				     : "=a"(old_val)
+				     : "r"(value), "m"(mtx->lock), "a"(old_val)
+				     : "memory");
 
 		if (old_val != 0) {
 			/* Contention on the mutex */
@@ -486,11 +476,10 @@ void mutex_unlock(struct mutex *mtx)
 	uint32_t old_val = 1, val = 0;
 	task_ *tsk = current_task;
 
-	__asm__ __volatile__(
-			ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
-			: "=a" (old_val)
-			: "r" (val), "m" (mtx->lock), "a" (old_val)
-			: "memory");
+	__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
+			     : "=a"(old_val)
+			     : "r"(val), "m"(mtx->lock), "a"(old_val)
+			     : "memory");
 	if (old_val == 1)
 		waiters = mtx->waiters;
 	/* else? Does unlock fail - what to do then ? */
@@ -532,13 +521,13 @@ void task_print_list(void)
 		if (IS_ENABLED(CONFIG_FPU)) {
 			char use_fpu = tasks[i].use_fpu ? 'Y' : 'N';
 
-			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d %c\n",
-				 i, is_ready, task_get_name(i),
+			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d %c\n", i,
+				 is_ready, task_get_name(i),
 				 (int)tasks[i].events, tasks[i].runtime,
 				 stackused, tasks_init[i].stack_size, use_fpu);
 		} else {
-			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n",
-				 i, is_ready, task_get_name(i),
+			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i,
+				 is_ready, task_get_name(i),
 				 (int)tasks[i].events, tasks[i].runtime,
 				 stackused, tasks_init[i].stack_size);
 		}
@@ -547,7 +536,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 	task_print_list();
 
@@ -577,12 +566,9 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-__maybe_unused
-static int command_task_ready(int argc, char **argv)
+__maybe_unused static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -596,8 +582,7 @@ static int command_task_ready(int argc, char **argv)
 }
 
 #ifdef CONFIG_CMD_TASKREADY
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -606,7 +591,7 @@ void task_pre_init(void)
 	int i, cs;
 	uint32_t *stack_next = (uint32_t *)task_stacks;
 
-	__asm__ __volatile__ ("movl %%cs, %0":"=r" (cs));
+	__asm__ __volatile__("movl %%cs, %0" : "=r"(cs));
 
 	/* Fill the task memory with initial values */
 	for (i = 0; i < TASK_ID_COUNT; i++) {
@@ -638,12 +623,12 @@ void task_pre_init(void)
 		sp[7] = 0xea;	/* EAX */
 #endif
 		/* For IRET */
-		sp[8] = tasks_init[i].pc;	/* pc */
+		sp[8] = tasks_init[i].pc; /* pc */
 		sp[9] = cs;
 		sp[10] = INITIAL_EFLAGS;
 
-		sp[11] = (uint32_t) task_exit_trap;
-		sp[12] = tasks_init[i].r0;	/* task argument */
+		sp[11] = (uint32_t)task_exit_trap;
+		sp[12] = tasks_init[i].r0; /* task argument */
 		sp[13] = 0x00;
 		sp[14] = 0x00;
 		sp[15] = 0x00;
@@ -656,7 +641,8 @@ void task_pre_init(void)
 				0x00, 0x00, /* Status[0-15] */
 				0xff, 0xff, /* unused */
 				0xff, 0xff, /* Tag[0-15] */
-				0xff, 0xff};/* unused */
+				0xff, 0xff
+			}; /* unused */
 
 			/* Copy default x86 FPU state for each task */
 			memcpy(tasks[i].fp_ctx, default_fp_ctx,
diff --git a/core/minute-ia/task_defs.h b/core/minute-ia/task_defs.h
index 18458b1533..dac80e0eb9 100644
--- a/core/minute-ia/task_defs.h
+++ b/core/minute-ia/task_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,9 @@
 #define __CROS_EC_TASK_DEFS_H
 
 #ifdef CONFIG_FPU
-#define FPU_CTX_SZ		108  /* 28 bytes header + 80 bytes registers */
-#define USE_FPU_OFFSET		20   /* offsetof(task_, use_fpu */
-#define FPU_CTX_OFFSET		24   /* offsetof(task_, fp_ctx) */
+#define FPU_CTX_SZ 108 /* 28 bytes header + 80 bytes registers */
+#define USE_FPU_OFFSET 20 /* offsetof(task_, use_fpu */
+#define FPU_CTX_OFFSET 24 /* offsetof(task_, fp_ctx) */
 
 /*
  * defines for inline asm
@@ -18,11 +18,11 @@
 #include "atomic.h"
 #include "common.h"
 
-#define USE_FPU_OFFSET_STR	STRINGIFY(USE_FPU_OFFSET)	/* "20" */
-#define FPU_CTX_OFFSET_STR	STRINGIFY(FPU_CTX_OFFSET)	/* "24" */
+#define USE_FPU_OFFSET_STR STRINGIFY(USE_FPU_OFFSET) /* "20" */
+#define FPU_CTX_OFFSET_STR STRINGIFY(FPU_CTX_OFFSET) /* "24" */
 
-asm (".equ USE_FPU_OFFSET, "USE_FPU_OFFSET_STR);
-asm (".equ FPU_CTX_OFFSET, "FPU_CTX_OFFSET_STR);
+asm(".equ USE_FPU_OFFSET, " USE_FPU_OFFSET_STR);
+asm(".equ FPU_CTX_OFFSET, " FPU_CTX_OFFSET_STR);
 
 #endif
 #endif /* CONFIG_FPU */
@@ -34,12 +34,12 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;	/* Saved stack pointer for context switch */
-		atomic_t events;	/* Bitmaps of received events */
-		uint64_t runtime;	/* Time spent in task */
-		uint32_t *stack;	/* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 #ifdef CONFIG_FPU
-		uint32_t use_fpu;	/* set if task uses FPU */
+		uint32_t use_fpu; /* set if task uses FPU */
 		uint8_t fp_ctx[FPU_CTX_SZ]; /* x87 FPU context */
 #endif
 	};
@@ -50,7 +50,7 @@ void __switchto(void);
 void sw_irq_handler(void);
 
 /* Only the IF bit is set so tasks start with interrupts enabled. */
-#define INITIAL_EFLAGS		(0x200UL)
+#define INITIAL_EFLAGS (0x200UL)
 
 /* LAPIC ICR bit fields
  *	7:0	- vector
@@ -61,7 +61,7 @@ void sw_irq_handler(void);
  *	15	- Trigger mode (0 = edge)
  *	20:18	- Destination (1 = self)
  */
-#define LAPIC_ICR_BITS		0x44000
+#define LAPIC_ICR_BITS 0x44000
 
 #endif /* __ASSEMBLER__ */
 #endif /* __CROS_EC_TASK_DEFS_H */
diff --git a/core/minute-ia/toolchain.mk b/core/minute-ia/toolchain.mk
new file mode 100644
index 0000000000..ed7ebfb2c8
--- /dev/null
+++ b/core/minute-ia/toolchain.mk
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Select Minute-IA bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\
+	/opt/coreboot-sdk/bin/i386-elf-)
diff --git a/core/nds32/__builtin.c b/core/nds32/__builtin.c
index 7b1d5eea62..ae8aa4b053 100644
--- a/core/nds32/__builtin.c
+++ b/core/nds32/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/__divdi3.S b/core/nds32/__divdi3.S
index d86e8f6273..36fe00a917 100644
--- a/core/nds32/__divdi3.S
+++ b/core/nds32/__divdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/__libsoftfpu.S b/core/nds32/__libsoftfpu.S
index 672e6bbb3d..3f2e60767f 100644
--- a/core/nds32/__libsoftfpu.S
+++ b/core/nds32/__libsoftfpu.S
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/__muldi3.S b/core/nds32/__muldi3.S
index ef4a491183..0e766de3cb 100644
--- a/core/nds32/__muldi3.S
+++ b/core/nds32/__muldi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/__udivdi3.S b/core/nds32/__udivdi3.S
index 4cb3b058fe..624faff2c5 100644
--- a/core/nds32/__udivdi3.S
+++ b/core/nds32/__udivdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h
index 592834faae..746093c919 100644
--- a/core/nds32/atomic.h
+++ b/core/nds32/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -85,4 +85,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return ret;
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/nds32/build.mk b/core/nds32/build.mk
index ddd65c680b..7790b96009 100644
--- a/core/nds32/build.mk
+++ b/core/nds32/build.mk
@@ -1,17 +1,11 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Andestar v3m architecture core OS files build
 #
 
-# Set coreboot-sdk as the default toolchain for nds32
-NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
-
-# Select Andes bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
-
 # CPU specific compilation flags
 CFLAGS_CPU+=-march=v3m -Os
 LDFLAGS_EXTRA+=-mrelax
diff --git a/core/nds32/config_core.h b/core/nds32/config_core.h
index 7670e5cfad..096b244643 100644
--- a/core/nds32/config_core.h
+++ b/core/nds32/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c
index 6a3f3b5bc4..cfdddb334e 100644
--- a/core/nds32/cpu.c
+++ b/core/nds32/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,5 +12,5 @@ void cpu_init(void)
 {
 	/* DLM initialization is done in init.S */
 	/* Global interrupt enable */
-	asm volatile ("setgie.e");
+	asm volatile("setgie.e");
 }
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
index 3bd5a93efc..54d1a243ba 100644
--- a/core/nds32/cpu.h
+++ b/core/nds32/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,9 +15,9 @@
 #define TASK_SCRATCHPAD_SIZE (18)
 
 /* Process Status Word bits */
-#define PSW_GIE		BIT(0) /* Global Interrupt Enable */
-#define PSW_INTL_SHIFT	1        /* Interrupt Stack Level */
-#define PSW_INTL_MASK	(0x3 << PSW_INTL_SHIFT)
+#define PSW_GIE BIT(0) /* Global Interrupt Enable */
+#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
+#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
 
 #ifndef __ASSEMBLER__
 
@@ -26,28 +26,28 @@
 /* write Process Status Word privileged register */
 static inline void set_psw(uint32_t val)
 {
-	asm volatile ("mtsr %0, $PSW" : : "r"(val));
+	asm volatile("mtsr %0, $PSW" : : "r"(val));
 }
 
 /* read Process Status Word privileged register */
 static inline uint32_t get_psw(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $PSW" : "=r"(ret));
+	asm volatile("mfsr %0, $PSW" : "=r"(ret));
 	return ret;
 }
 
 /* write Interruption Program Counter privileged register */
 static inline void set_ipc(uint32_t val)
 {
-	asm volatile ("mtsr %0, $IPC" : : "r"(val));
+	asm volatile("mtsr %0, $IPC" : : "r"(val));
 }
 
 /* read Interruption Program Counter privileged register */
 static inline uint32_t get_ipc(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $IPC" : "=r"(ret));
+	asm volatile("mfsr %0, $IPC" : "=r"(ret));
 	return ret;
 }
 
@@ -55,7 +55,7 @@ static inline uint32_t get_ipc(void)
 static inline uint32_t get_itype(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
+	asm volatile("mfsr %0, $ITYPE" : "=r"(ret));
 	return ret;
 }
 
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S
index fbc5ceaafd..87f6d2041a 100644
--- a/core/nds32/ec.lds.S
+++ b/core/nds32/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -185,6 +185,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -263,6 +267,12 @@ SECTIONS
 		__bss_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated RAM,
 		 * so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/nds32/include/fpu.h b/core/nds32/include/fpu.h
index 4f3efc2e5a..80c3395d14 100644
--- a/core/nds32/include/fpu.h
+++ b/core/nds32/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,4 +11,4 @@
 float sqrtf(float x);
 float fabsf(float x);
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/nds32/init.S b/core/nds32/init.S
index 159f3709d3..648e3d8183 100644
--- a/core/nds32/init.S
+++ b/core/nds32/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/irq_chip.h b/core/nds32/irq_chip.h
index ca517558b3..a339bb516c 100644
--- a/core/nds32/irq_chip.h
+++ b/core/nds32/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h
index 7e404b5d0c..b1feaa44c3 100644
--- a/core/nds32/irq_handler.h
+++ b/core/nds32/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,12 +15,12 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	static void __keep routine(void);				\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority)                                   \
+	static void __keep routine(void);                                     \
+	void IRQ_HANDLER(CPU_INT(irq))(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));                   \
+	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))           \
+		__attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+								priority }
 
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/nds32/math.c b/core/nds32/math.c
index 496fcc0e5d..d0c8fc5c33 100644
--- a/core/nds32/math.c
+++ b/core/nds32/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,19 @@ union ieee_float_shape_type {
 };
 
 /* Get a 32 bit int from a float.  */
-#define GET_FLOAT_WORD(i, d) \
-	do { \
+#define GET_FLOAT_WORD(i, d)                      \
+	do {                                      \
 		union ieee_float_shape_type gf_u; \
-		gf_u.value = (d); \
-		(i) = gf_u.word; \
+		gf_u.value = (d);                 \
+		(i) = gf_u.word;                  \
 	} while (0)
 
 /* Set a float from a 32 bit int. */
-#define SET_FLOAT_WORD(d, i) \
-	do { \
+#define SET_FLOAT_WORD(d, i)                      \
+	do {                                      \
 		union ieee_float_shape_type sf_u; \
-		sf_u.word = (i); \
-		(d) = sf_u.value; \
+		sf_u.word = (i);                  \
+		(d) = sf_u.value;                 \
 	} while (0)
 
 float fabsf(float x)
diff --git a/core/nds32/panic.c b/core/nds32/panic.c
index 70e2cae3e0..a1eca1574f 100644
--- a/core/nds32/panic.c
+++ b/core/nds32/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 /* General purpose register (r6) for saving software panic reason */
 #define SOFT_PANIC_GPR_REASON 6
 /* General purpose register (r7) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   7
+#define SOFT_PANIC_GPR_INFO 7
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 /**
@@ -46,7 +46,7 @@
  * All other exceptions not in the abovetable should have the INST field of
  * the ITYPE register set to 0.
  */
-static const char * const itype_inst[2] = {
+static const char *const itype_inst[2] = {
 	"a data memory access",
 	"an instruction fetch access",
 };
@@ -54,7 +54,7 @@ static const char * const itype_inst[2] = {
 /**
  * bit[3-0] @ ITYPE, general exception type information.
  */
-static const char * const itype_exc_type[16] = {
+static const char *const itype_exc_type[16] = {
 	"Alignment check",
 	"Reserved instruction",
 	"Trap",
@@ -78,8 +78,8 @@ static const char * const itype_exc_type[16] = {
 #ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	asm volatile ("mov55  $r6, %0" : : "r"(reason));
-	asm volatile ("mov55  $r7, %0" : : "r"(info));
+	asm volatile("mov55  $r6, %0" : : "r"(reason));
+	asm volatile("mov55  $r7, %0" : : "r"(info));
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
@@ -94,7 +94,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	 * If it was called earlier (eg. when saving nds_n8.ipc) calling it
 	 * once again won't remove any data
 	 */
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t warning_ipc;
 	uint32_t *regs;
 
@@ -121,7 +121,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *regs;
 
 	if (pdata && pdata->struct_version == 2) {
@@ -136,17 +136,17 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 #endif /* CONFIG_SOFTWARE_PANIC */
 
 static void print_panic_information(uint32_t *regs, uint32_t itype,
-					uint32_t ipc, uint32_t ipsw)
+				    uint32_t ipc, uint32_t ipsw)
 {
 	panic_printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
+	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n", regs[0], regs[1],
+		     regs[2], regs[3]);
+	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n", regs[4], regs[5],
+		     regs[6], regs[7]);
+	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n", regs[8], regs[9],
+		     regs[10], regs[11]);
+	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n", regs[12],
+		     regs[13], regs[14], regs[15]);
 	panic_printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
 	if ((ipsw & PSW_INTL_MASK) == (2 << PSW_INTL_SHIFT)) {
 		/* 2nd level exception */
@@ -161,16 +161,16 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 	if (panic_sw_reason_is_valid(regs[SOFT_PANIC_GPR_REASON])) {
 #ifdef CONFIG_SOFTWARE_PANIC
 		panic_printf("Software panic reason %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-					  PANIC_SW_BASE)]);
+			     panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					       PANIC_SW_BASE)]);
 		panic_printf("Software panic info 0x%x\n",
-			regs[SOFT_PANIC_GPR_INFO]);
+			     regs[SOFT_PANIC_GPR_INFO]);
 #endif
 	} else {
 		panic_printf("Exception type: General exception [%s]\n",
-			itype_exc_type[(itype & 0xf)]);
+			     itype_exc_type[(itype & 0xf)]);
 		panic_printf("Exception is caused by %s\n",
-			itype_inst[(itype & BIT(4))]);
+			     itype_inst[(itype & BIT(4))]);
 	}
 #endif
 }
@@ -178,7 +178,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 void report_panic(uint32_t *regs, uint32_t itype)
 {
 	int i;
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	pdata->magic = PANIC_DATA_MAGIC;
 	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
diff --git a/core/nds32/switch.S b/core/nds32/switch.S
index 13d1b14345..e7a8584ce5 100644
--- a/core/nds32/switch.S
+++ b/core/nds32/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/task.c b/core/nds32/task.c
index 5fc86d6050..d9ea6f191f 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -13,6 +14,7 @@
 #include "intc.h"
 #include "irq_chip.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
@@ -24,10 +26,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		atomic_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -42,11 +44,9 @@ CONFIG_TEST_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -54,12 +54,12 @@ static const char * const task_names[] = {
 static int task_will_switch;
 static uint32_t exc_sub_time;
 static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(void);
@@ -80,7 +80,7 @@ void __idle(void)
 		/* doze mode */
 		IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
 #endif
-		asm volatile ("dsb");
+		asm volatile("dsb");
 		/*
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
@@ -100,20 +100,18 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 #undef TASK
 
 /* Contexts for all tasks */
@@ -122,20 +120,16 @@ static task_ tasks[TASK_ID_COUNT];
 BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
 /* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+	__attribute__((section(".bss.task_scratchpad")));
 
 task_ *current_task = (task_ *)scratchpad;
 
@@ -167,7 +161,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-int start_called;  /* Has task swapping started */
+int start_called; /* Has task swapping started */
 
 /* interrupt number of sw interrupt */
 static int sw_int_num;
@@ -213,22 +207,22 @@ void __ram_code interrupt_disable(void)
 {
 	/* Mask all interrupts, only keep division by zero exception */
 	uint32_t val = BIT(30);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
-	asm volatile ("dsb");
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("dsb");
 }
 
 void __ram_code interrupt_enable(void)
 {
 	/* Enable HW2 ~ HW15 and division by zero exception interrupts */
 	uint32_t val = (BIT(30) | 0xFFFC);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
 inline bool is_interrupt_enabled(void)
 {
 	uint32_t val = 0;
 
-	asm volatile ("mfsr %0, $INT_MASK" : "=r"(val));
+	asm volatile("mfsr %0, $INT_MASK" : "=r"(val));
 
 	/* Interrupts are enabled if any of HW2 ~ HW15 is enabled */
 	return val & 0xFFFC;
@@ -267,7 +261,7 @@ int task_start_called(void)
  * Also includes emulation of software triggering interrupt vector
  */
 void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
+				       int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -307,7 +301,7 @@ task_ *next_sched_task(void)
 #ifdef CONFIG_TASK_PROFILING
 	if (current_task != new_task) {
 		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
+			(exc_start_time - exc_end_time - exc_sub_time);
 		task_will_switch = 1;
 	}
 #endif
@@ -348,7 +342,7 @@ volatile int ec_int;
 void __ram_code start_irq_handler(void)
 {
 	/* save r0, r1, and r2 for syscall */
-	asm volatile ("smw.adm $r0, [$sp], $r2, 0");
+	asm volatile("smw.adm $r0, [$sp], $r2, 0");
 	/* If this is a SW interrupt */
 	if (get_itype() & 8)
 		ec_int = sw_int_num;
@@ -369,7 +363,7 @@ void __ram_code start_irq_handler(void)
 		irq_dist[ec_int]++;
 #endif
 	/* restore r0, r1, and r2 */
-	asm volatile ("lmw.bim $r0, [$sp], $r2, 0");
+	asm volatile("lmw.bim $r0, [$sp], $r2, 0");
 }
 
 void end_irq_handler(void)
@@ -380,7 +374,7 @@ void end_irq_handler(void)
 	 * save r0 and fp (fp for restore r0-r5, r15, fp, lp and sp
 	 * while interrupt exit.
 	 */
-	asm volatile ("smw.adm $r0, [$sp], $r0, 8");
+	asm volatile("smw.adm $r0, [$sp], $r0, 8");
 
 	t = get_time().le.lo;
 	p = t - exc_start_time;
@@ -395,7 +389,7 @@ void end_irq_handler(void)
 	}
 
 	/* restore r0 and fp */
-	asm volatile ("lmw.bim $r0, [$sp], $r0, 8");
+	asm volatile("lmw.bim $r0, [$sp], $r0, 8");
 #endif
 }
 
@@ -483,37 +477,36 @@ uint32_t __ram_code read_clear_int_mask(void)
 {
 	uint32_t int_mask, int_dis = BIT(30);
 
-	asm volatile(
-		"mfsr %0, $INT_MASK\n\t"
-		"mtsr %1, $INT_MASK\n\t"
-		"dsb\n\t"
-		: "=&r"(int_mask)
-		: "r"(int_dis));
+	asm volatile("mfsr %0, $INT_MASK\n\t"
+		     "mtsr %1, $INT_MASK\n\t"
+		     "dsb\n\t"
+		     : "=&r"(int_mask)
+		     : "r"(int_dis));
 
 	return int_mask;
 }
 
 void __ram_code set_int_mask(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
 static void set_int_priority(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_PRI" : : "r"(val));
+	asm volatile("mtsr %0, $INT_PRI" : : "r"(val));
 }
 
 uint32_t get_int_ctrl(void)
 {
 	uint32_t ret;
 
-	asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret));
+	asm volatile("mfsr %0, $INT_CTRL" : "=r"(ret));
 	return ret;
 }
 
 void set_int_ctrl(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val));
+	asm volatile("mtsr %0, $INT_CTRL" : : "r"(val));
 }
 
 void task_enable_all_tasks(void)
@@ -599,7 +592,7 @@ static void ivic_init_irqs(void)
 	for (i = 0; i < exc_calls; i++) {
 		uint8_t irq = __irqprio[i].irq;
 		uint8_t prio = __irqprio[i].priority;
-		all_priorities |= (prio & 0x3)  << (irq * 2);
+		all_priorities |= (prio & 0x3) << (irq * 2);
 	}
 	set_int_priority(all_priorities);
 }
@@ -685,7 +678,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -715,11 +708,9 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -731,8 +722,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 
 void task_pre_init(void)
@@ -755,11 +745,11 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[7] = tasks_init[i].r0;           /* r0 */
-		sp[15] = (uint32_t)task_exit_trap;  /* lr */
-		sp[1] = tasks_init[i].pc;           /* pc */
-		sp[0] = 0x70009;                    /* psw */
-		sp[16] = (uint32_t)(sp + 17);       /* sp */
+		sp[7] = tasks_init[i].r0; /* r0 */
+		sp[15] = (uint32_t)task_exit_trap; /* lr */
+		sp[1] = tasks_init[i].pc; /* pc */
+		sp[0] = 0x70009; /* psw */
+		sp[16] = (uint32_t)(sp + 17); /* sp */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/nds32/toolchain.mk b/core/nds32/toolchain.mk
new file mode 100644
index 0000000000..e2405d3054
--- /dev/null
+++ b/core/nds32/toolchain.mk
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Set coreboot-sdk as the default toolchain for nds32
+NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
+
+# Select Andes bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
diff --git a/core/riscv-rv32i/__builtin.c b/core/riscv-rv32i/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/riscv-rv32i/__builtin.c
+++ b/core/riscv-rv32i/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/riscv-rv32i/__it8xxx2_arithmetic.S b/core/riscv-rv32i/__it8xxx2_arithmetic.S
index 8e477863fc..de6dd220ad 100644
--- a/core/riscv-rv32i/__it8xxx2_arithmetic.S
+++ b/core/riscv-rv32i/__it8xxx2_arithmetic.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The ChromiumOS Authors.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/atomic.h b/core/riscv-rv32i/atomic.h
index 4d6114cd53..edd27f20e8 100644
--- a/core/riscv-rv32i/atomic.h
+++ b/core/riscv-rv32i/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,4 +53,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk
index 7e5ce0e8a7..99171a422d 100644
--- a/core/riscv-rv32i/build.mk
+++ b/core/riscv-rv32i/build.mk
@@ -1,15 +1,11 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # RISC-V core OS files build
 #
 
-# Select RISC-V bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
-	/opt/coreboot-sdk/bin/riscv64-elf-)
-
 # Enable FPU extension if config option of FPU is enabled.
 _FPU_EXTENSION=$(if $(CONFIG_FPU),f,)
 # Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled.
diff --git a/core/riscv-rv32i/config_core.h b/core/riscv-rv32i/config_core.h
index fe6135683d..2adcd2783f 100644
--- a/core/riscv-rv32i/config_core.h
+++ b/core/riscv-rv32i/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/riscv-rv32i/cpu.c b/core/riscv-rv32i/cpu.c
index fd18896846..911d170801 100644
--- a/core/riscv-rv32i/cpu.c
+++ b/core/riscv-rv32i/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,5 +10,5 @@
 void cpu_init(void)
 {
 	/* bit3: Global interrupt enable (M-mode) */
-	asm volatile ("csrsi mstatus, 0x8");
+	asm volatile("csrsi mstatus, 0x8");
 }
diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h
index e46b893ad6..39ee3fe126 100644
--- a/core/riscv-rv32i/cpu.h
+++ b/core/riscv-rv32i/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,7 +25,7 @@
 /* write Exception Program Counter register */
 static inline void set_mepc(uint32_t val)
 {
-	asm volatile ("csrw mepc, %0" : : "r"(val));
+	asm volatile("csrw mepc, %0" : : "r"(val));
 }
 
 /* read Exception Program Counter register */
@@ -33,7 +33,7 @@ static inline uint32_t get_mepc(void)
 {
 	uint32_t ret;
 
-	asm volatile ("csrr %0, mepc" : "=r"(ret));
+	asm volatile("csrr %0, mepc" : "=r"(ret));
 	return ret;
 }
 
@@ -42,7 +42,7 @@ static inline uint32_t get_mcause(void)
 {
 	uint32_t ret;
 
-	asm volatile ("csrr %0, mcause" : "=r"(ret));
+	asm volatile("csrr %0, mcause" : "=r"(ret));
 	return ret;
 }
 
diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S
index 1e629a5779..e62a7d1427 100644
--- a/core/riscv-rv32i/ec.lds.S
+++ b/core/riscv-rv32i/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -233,6 +233,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -334,6 +338,12 @@ SECTIONS
 		__bss_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated RAM,
 		 * so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/riscv-rv32i/include/fpu.h b/core/riscv-rv32i/include/fpu.h
index 25d83f228f..da48139d1c 100644
--- a/core/riscv-rv32i/include/fpu.h
+++ b/core/riscv-rv32i/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 float sqrtf(float x);
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S
index 8ee5479e0e..6231ad94c0 100644
--- a/core/riscv-rv32i/init.S
+++ b/core/riscv-rv32i/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/irq_chip.h b/core/riscv-rv32i/irq_chip.h
index 45cabf346e..b45a754f45 100644
--- a/core/riscv-rv32i/irq_chip.h
+++ b/core/riscv-rv32i/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/irq_handler.h b/core/riscv-rv32i/irq_handler.h
index 6fe7769684..b980e8e0bc 100644
--- a/core/riscv-rv32i/irq_handler.h
+++ b/core/riscv-rv32i/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,12 +20,12 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	static void __keep routine(void);				\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority)                                   \
+	static void __keep routine(void);                                     \
+	void IRQ_HANDLER(CPU_INT(irq))(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));                   \
+	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))           \
+		__attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+								priority }
 
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c
index 591a67eb8f..425814f185 100644
--- a/core/riscv-rv32i/math.c
+++ b/core/riscv-rv32i/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,7 @@
 /* Single precision floating point square root. */
 float sqrtf(float x)
 {
-	asm volatile (
-		"fsqrt.s %0, %1"
-		: "=f" (x)
-		: "f" (x));
+	asm volatile("fsqrt.s %0, %1" : "=f"(x) : "f"(x));
 
 	return x;
 }
diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c
index 5860fba072..a2ce9213d9 100644
--- a/core/riscv-rv32i/panic.c
+++ b/core/riscv-rv32i/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 /**
  * bit[3-0] @ mcause, general exception type information.
  */
-static const char * const exc_type[16] = {
+static const char *const exc_type[16] = {
 	"Instruction address misaligned",
 	"Instruction access fault",
 	"Illegal instruction",
@@ -38,12 +38,12 @@ static const char * const exc_type[16] = {
 /* General purpose register (s0) for saving software panic reason */
 #define SOFT_PANIC_GPR_REASON 11
 /* General purpose register (s1) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   10
+#define SOFT_PANIC_GPR_INFO 10
 
 void software_panic(uint32_t reason, uint32_t info)
 {
-	asm volatile ("mv s0, %0" : : "r"(reason) : "s0");
-	asm volatile ("mv s1, %0" : : "r"(info)   : "s1");
+	asm volatile("mv s0, %0" : : "r"(reason) : "s0");
+	asm volatile("mv s1, %0" : : "r"(info) : "s1");
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
@@ -58,7 +58,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	 * If it was called earlier (eg. when saving riscv.mepc) calling it
 	 * once again won't remove any data
 	 */
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t warning_mepc;
 	uint32_t *regs;
 
@@ -85,7 +85,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *regs;
 
 	if (pdata && pdata->struct_version == 2) {
@@ -100,34 +100,34 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 #endif /* CONFIG_SOFTWARE_PANIC */
 
 static void print_panic_information(uint32_t *regs, uint32_t mcause,
-					uint32_t mepc)
+				    uint32_t mepc)
 {
 	panic_printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-		     regs[16], regs[17], regs[18], regs[19]);
-	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-		     regs[20], regs[21], regs[22], regs[23]);
-	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-		     regs[24], regs[25], regs[26], regs[27]);
-	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-		     regs[28], regs[29], regs[30], mepc);
+	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0],
+		     regs[1], regs[2], regs[3]);
+	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4],
+		     regs[5], regs[6], regs[7]);
+	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8],
+		     regs[9], regs[10], regs[11]);
+	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12],
+		     regs[13], regs[14], regs[15]);
+	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16],
+		     regs[17], regs[18], regs[19]);
+	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20],
+		     regs[21], regs[22], regs[23]);
+	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24],
+		     regs[25], regs[26], regs[27]);
+	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28],
+		     regs[29], regs[30], mepc);
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
 #ifdef CONFIG_SOFTWARE_PANIC
 		panic_printf("Software panic reason: %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-						PANIC_SW_BASE)]);
+			     panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					       PANIC_SW_BASE)]);
 		panic_printf("Software panic info:   %d\n",
-			regs[SOFT_PANIC_GPR_INFO]);
+			     regs[SOFT_PANIC_GPR_INFO]);
 #endif
 	} else {
 		panic_printf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
@@ -138,7 +138,7 @@ static void print_panic_information(uint32_t *regs, uint32_t mcause,
 void report_panic(uint32_t *regs)
 {
 	uint32_t i, mcause, mepc;
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	mepc = get_mepc();
 	mcause = get_mcause();
@@ -171,36 +171,36 @@ void panic_data_print(const struct panic_data *pdata)
 
 #ifdef CONFIG_PANIC_CONSOLE_OUTPUT
 static void ccprint_panic_information(uint32_t *regs, uint32_t mcause,
-					uint32_t mepc)
+				      uint32_t mepc)
 {
 	ccprintf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	ccprintf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	ccprintf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	ccprintf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	ccprintf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	ccprintf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-		     regs[16], regs[17], regs[18], regs[19]);
+	ccprintf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0], regs[1],
+		 regs[2], regs[3]);
+	ccprintf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4], regs[5],
+		 regs[6], regs[7]);
+	ccprintf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8], regs[9],
+		 regs[10], regs[11]);
+	ccprintf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12], regs[13],
+		 regs[14], regs[15]);
+	ccprintf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16], regs[17],
+		 regs[18], regs[19]);
 	cflush();
 
-	ccprintf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-		     regs[20], regs[21], regs[22], regs[23]);
-	ccprintf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-		     regs[24], regs[25], regs[26], regs[27]);
-	ccprintf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-		     regs[28], regs[29], regs[30], mepc);
+	ccprintf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20], regs[21],
+		 regs[22], regs[23]);
+	ccprintf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24], regs[25],
+		 regs[26], regs[27]);
+	ccprintf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28], regs[29],
+		 regs[30], mepc);
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
 #ifdef CONFIG_SOFTWARE_PANIC
 		ccprintf("Software panic reason: %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-						PANIC_SW_BASE)]);
+			 panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					   PANIC_SW_BASE)]);
 		ccprintf("Software panic info:   %d\n",
-			regs[SOFT_PANIC_GPR_INFO]);
+			 regs[SOFT_PANIC_GPR_INFO]);
 #endif /* CONFIG_SOFTWARE_PANIC */
 	} else {
 		ccprintf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S
index f58ac26e63..f8b88f9235 100644
--- a/core/riscv-rv32i/switch.S
+++ b/core/riscv-rv32i/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c
index edc31a872e..84415dcda9 100644
--- a/core/riscv-rv32i/task.c
+++ b/core/riscv-rv32i/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,12 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "cpu.h"
 #include "irq_chip.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
@@ -19,10 +21,10 @@ typedef struct {
 	 * Note that sp must be the first element in the task struct
 	 * for __switchto() to work.
 	 */
-	uint32_t sp;       /* Saved stack pointer for context switch */
-	atomic_t events;   /* Bitmaps of received events */
-	uint64_t runtime;  /* Time spent in task */
-	uint32_t *stack;   /* Start of stack */
+	uint32_t sp; /* Saved stack pointer for context switch */
+	atomic_t events; /* Bitmaps of received events */
+	uint64_t runtime; /* Time spent in task */
+	uint32_t *stack; /* Start of stack */
 } task_;
 
 /* Value to store in unused stack */
@@ -36,11 +38,9 @@ CONFIG_TEST_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -48,12 +48,12 @@ static const char * const task_names[] = {
 static int task_will_switch;
 static uint32_t exc_sub_time;
 static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(void);
@@ -96,41 +96,36 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.a0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.a0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t a0;
 	uint32_t pc;
 	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 #undef TASK
 
 /* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT] __attribute__ ((section(".bss.tasks")));
+static task_ tasks[TASK_ID_COUNT] __attribute__((section(".bss.tasks")));
 /* Validity checks about static task invariants */
 BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned) * 8));
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
 /* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+	__attribute__((section(".bss.task_scratchpad")));
 
 task_ *current_task = (task_ *)scratchpad;
 
@@ -162,7 +157,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-int start_called;  /* Has task swapping started */
+int start_called; /* Has task swapping started */
 
 /* in interrupt context */
 volatile bool in_interrupt;
@@ -188,22 +183,22 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 void __ram_code interrupt_disable(void)
 {
 	/* bit11: disable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrc mie, t0");
+	asm volatile("li t0, 0x800");
+	asm volatile("csrc mie, t0");
 }
 
 void __ram_code interrupt_enable(void)
 {
 	/* bit11: enable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrs  mie, t0");
+	asm volatile("li t0, 0x800");
+	asm volatile("csrs  mie, t0");
 }
 
 inline bool is_interrupt_enabled(void)
 {
 	int mie = 0;
 
-	asm volatile ("csrr %0, mie" : "=r"(mie));
+	asm volatile("csrr %0, mie" : "=r"(mie));
 
 	/* Check if MEIE bit is set in MIE register */
 	return mie & 0x800;
@@ -229,7 +224,7 @@ task_id_t __ram_code task_get_current(void)
 	return current_task - tasks;
 }
 
-atomic_t * __ram_code task_get_event_bitmap(task_id_t tskid)
+atomic_t *__ram_code task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 
@@ -247,7 +242,7 @@ int task_start_called(void)
  * Also includes emulation of software triggering interrupt vector
  */
 void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
+				       int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -279,14 +274,14 @@ void __ram_code __keep syscall_handler(int desched, task_id_t resched,
 	set_mepc(get_mepc() + 4);
 }
 
-task_ * __ram_code next_sched_task(void)
+task_ *__ram_code next_sched_task(void)
 {
 	task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
 
 #ifdef CONFIG_TASK_PROFILING
 	if (current_task != new_task) {
 		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
+			(exc_start_time - exc_end_time - exc_sub_time);
 		task_will_switch = 1;
 	}
 #endif
@@ -466,14 +461,14 @@ uint32_t __ram_code read_clear_int_mask(void)
 	uint32_t mie, meie = BIT(11);
 
 	/* Read and clear MEIE bit of MIE register. */
-	asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
+	asm volatile("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
 
 	return mie;
 }
 
 void __ram_code set_int_mask(uint32_t val)
 {
-	asm volatile ("csrw mie, %0" : : "r"(val));
+	asm volatile("csrw mie, %0" : : "r"(val));
 }
 
 void task_enable_all_tasks(void)
@@ -553,12 +548,12 @@ void __ram_code mutex_lock(struct mutex *mtx)
 	atomic_or(&mtx->waiters, id);
 
 	while (1) {
-		asm volatile (
+		asm volatile(
 			/* set lock value */
 			"li %0, 2\n\t"
 			/* attempt to acquire lock */
 			"amoswap.w.aq %0, %0, %1\n\t"
-			: "=&r" (locked), "+A" (mtx->lock));
+			: "=&r"(locked), "+A"(mtx->lock));
 		/* we got it ! */
 		if (!locked)
 			break;
@@ -576,9 +571,7 @@ void __ram_code mutex_unlock(struct mutex *mtx)
 	task_ *tsk = current_task;
 
 	/* give back the lock */
-	asm volatile (
-		"amoswap.w.aqrl zero, zero, %0\n\t"
-		: "+A" (mtx->lock));
+	asm volatile("amoswap.w.aqrl zero, zero, %0\n\t" : "+A"(mtx->lock));
 	waiters = mtx->waiters;
 
 	while (waiters) {
@@ -618,7 +611,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	unsigned int total = 0;
@@ -648,11 +641,9 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -664,8 +655,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 
 void task_pre_init(void)
@@ -688,9 +678,10 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[TASK_SCRATCHPAD_SIZE-2] = tasks_init[i].a0;         /* a0 */
-		sp[TASK_SCRATCHPAD_SIZE-1] = (uint32_t)task_exit_trap; /* ra */
-		sp[0] = tasks_init[i].pc;  /* pc/mepc */
+		sp[TASK_SCRATCHPAD_SIZE - 2] = tasks_init[i].a0; /* a0 */
+		sp[TASK_SCRATCHPAD_SIZE - 1] = (uint32_t)task_exit_trap; /* ra
+									  */
+		sp[0] = tasks_init[i].pc; /* pc/mepc */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/riscv-rv32i/toolchain.mk b/core/riscv-rv32i/toolchain.mk
new file mode 100644
index 0000000000..aa833d1ca3
--- /dev/null
+++ b/core/riscv-rv32i/toolchain.mk
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Select RISC-V bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
+	/opt/coreboot-sdk/bin/riscv64-elf-)
author	Tom Hughes <tomhughes@chromium.org>	2022-09-21 14:10:01 -0700
committer	Tom Hughes <tomhughes@chromium.org>	2022-09-22 12:49:33 -0700
commit	2bcf863b492fe7ed8105c853814dba6ed32ba719 (patch)
tree	fcf6ce5810f9ff9e3c8cce434812dd75492269ed /core
parent	e5fb0b9ba488614b5684e640530f00821ab7b943 (diff)
parent	28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff)
download	chrome-ec-2bcf863b492fe7ed8105c853814dba6ed32ba719.tar.gz