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| author | Dino Li <Dino.Li@ite.com.tw> | 2020-03-18 11:07:22 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-03-21 04:49:34 +0000 |
| commit | 45e52682c29e0e08f25b0572ed16ad49cf559ee4 (patch) | |
| tree | e4d6b9a95aa2f89cac51eef92399d672e885bc24 /core | |
| parent | 777f57c6f406292435dd7f836914e3f7ad435ed5 (diff) | |
| download | chrome-ec-45e52682c29e0e08f25b0572ed16ad49cf559ee4.tar.gz | |
chip/it8xxx2: add support IT81302 and IT81202
IT81302 (144-pins package) and IT81202 (128-pins package) chips belong
to it8xxx2 family. So we apply the same chip options of it83202bx
(except ADC pin order config option) and setup the correct flash size,
ram size, and ram base.
With this change, we are able to build FW image with IT81202 or IT81302
chip variant.
BUG=none
BRANCH=none
TEST=EC boots and test console commands
(version, sysinfo, sysjump, flasherase, flashwrite, and flashread)
on IT81202 EVB.
Hibernate EC and then press servo board's COLD_RST_L to reset EC.
EC reboots.
Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/riscv-rv32i/init.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S index 11b1dba1f8..de98846686 100644 --- a/core/riscv-rv32i/init.S +++ b/core/riscv-rv32i/init.S @@ -7,6 +7,13 @@ #include "config.h" +/* + * ILM/DLM size register. + * bit[3-0] ILM size: + * 7: 512K byte (default setting), 8: 1M byte + */ +#define IT83XX_GCTRL_EIDSR 0xf02031 + .macro vector name .set \name\()_handler, unhandled_ec_irq .weak \name\()_handler @@ -266,6 +273,14 @@ __reset: /* The M-mode handles interrupt/exception */ csrwi mideleg, 0 csrwi medeleg, 0 +#ifdef IT83XX_CHIP_FLASH_SIZE_1MB + /* ILM size is 1M bytes */ + la t0, IT83XX_GCTRL_EIDSR + lb t1, 0(t0) + andi t1, t1, 0xf0 + ori t1, t1, 0x8 + sb t1, 0(t0) +#endif /* Clear BSS */ la t0, __bss_start la t1, __bss_end |