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authorDino Li <Dino.Li@ite.com.tw>2020-11-18 16:41:49 +0800
committerCommit Bot <commit-bot@chromium.org>2020-12-17 03:23:42 +0000
commit5003532c49588983d235f7ffcb6c59a53c965378 (patch)
tree98b7613ef1f16b7a7776463549cd7daffecfb0ac /core
parentde6289da947f23240b9234717799bb83250a2a72 (diff)
downloadchrome-ec-5003532c49588983d235f7ffcb6c59a53c965378.tar.gz
it8xxx2: enable ILM0
This change enable ILM0 for it8xxx2 series, so we can pull more code into static cache to save latency of fetching code from flash. BUG=b:171172053 BRANCH=none TEST=Check timestamp of "Inits done" on asurada: Before the change was made, we got the timestamp is: [0.004408 Inits done] With this change, the timestamp is changed to: [0.003843 Inits done] Change-Id: Ie7a241bed2f926fd0034cecaf5d8e8183ca16d2e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563056 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'core')
-rw-r--r--core/riscv-rv32i/ec.lds.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S
index 0280c6ee9c..e849095d92 100644
--- a/core/riscv-rv32i/ec.lds.S
+++ b/core/riscv-rv32i/ec.lds.S
@@ -82,6 +82,12 @@ SECTIONS
ASSERT((__flash_dma_size < IT83XX_ILM_BLOCK_SIZE),
"__flash_dma_size < IT83XX_ILM_BLOCK_SIZE");
. = ALIGN(IT83XX_ILM_BLOCK_SIZE);
+ __ilm0_ram_code = .;
+ OUTDIR/chip/it83xx/i2c.o (.text*)
+ OUTDIR/chip/it83xx/i2c.o (.rodata)
+ OUTDIR/chip/it83xx/hwtimer.o (.text*)
+ OUTDIR/chip/it83xx/hwtimer.o (.rodata)
+ . = ALIGN(16);
#endif
*(.text*)
. = ALIGN(4);