Provide 'is_interrupt_enabled' function for all cores

Add a function that will provide information if interrupts are enabled.
This information will be used to fix shortcomings in common code for
UART buffering and usleep().

BUG=b:190597666
BRANCH=none
TEST=make -j buildall
TEST=make runhosttests
TEST=Note for running tests: this patch only adds function
     implementation so, to test this it is necessary to add some code
     which uses the function eg. console command which prints
     information if interrupt is enabled.

     Minute-ia core: It is necessary to compile firmware for
     ISH (Intel Sensor Hub) which is available on drallion board
     (eg. chromeos6-row1-rack9-host19). Firmware must be placed in
     /lib/firmware/intel/drallion_ish.bin (partition must be writeable,
     if not use /usr/share/vboot/bin/make_dev_ssd.sh on DUT tu unlock
     it, don't forget about reboot). After copying firmware to
     /lib/firmware/intel/ it is necessary to reboot DUT. After reboot
     use `ectool --name=cros_ish version` to check if correct version
     is running.

     NDS32 core. This core is used in it8320dx chip which is present in
     ampton (octopus family). EC can be compiled using
     'make BOARD=ampton' and flashed using
     'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to
     be disabled using 'set_gbb_flags.sh 0x200'

     Riscv-rv32i core, hayato (asurada family) uses it81202 as EC which
     is based on risc-v. EC can be compiled using 'make BOARD=hayato'
     and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC
     software sync needs to be disabled using 'set_gbb_flags.sh 0x200'

     Cortex-M, this is the most common core. Just compile EC for
     platform which contains Cortex-M core (eg. bloonchipper) and test
     if it works.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I502553cd57e6ce897d5845a3aad01a44a9058405
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953227
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Tested-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

6 files changed, 57 insertions, 0 deletions

diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index b88baf4511..e64063dc15 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -227,6 +227,16 @@ void interrupt_enable(void)
 	asm("cpsie i");
 }
 
+inline int is_interrupt_enabled(void)
+{
+	int primask;
+
+	/* Interrupts are enabled when PRIMASK bit is 0 */
+	asm("mrs %0, primask":"=r"(primask));
+
+	return !(primask & 0x1);
+}
+
 inline int in_interrupt_context(void)
 {
 	int ret;
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index 16922e10eb..5c9893ace8 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -161,6 +161,16 @@ void interrupt_enable(void)
 	asm("cpsie i");
 }
 
+inline int is_interrupt_enabled(void)
+{
+	int primask;
+
+	/* Interrupts are enabled when PRIMASK bit is 0 */
+	asm("mrs %0, primask":"=r"(primask));
+
+	return !(primask & 0x1);
+}
+
 inline int in_interrupt_context(void)
 {
 	int ret;
diff --git a/core/host/task.c b/core/host/task.c
index 36cb3467c0..be7ed3c579 100644
--- a/core/host/task.c
+++ b/core/host/task.c
@@ -138,6 +138,11 @@ test_mockable void interrupt_enable(void)
 	pthread_mutex_unlock(&interrupt_lock);
 }
 
+inline int is_interrupt_enabled(void)
+{
+	return !interrupt_disabled;
+}
+
 static void _task_execute_isr(int sig)
 {
 	in_interrupt = 1;
diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c
index 0cdc8a41e5..fdbe37485b 100644
--- a/core/minute-ia/task.c
+++ b/core/minute-ia/task.c
@@ -173,6 +173,18 @@ void interrupt_enable(void)
 	__asm__ __volatile__ ("sti");
 }
 
+inline int is_interrupt_enabled(void)
+{
+	uint32_t eflags = 0;
+
+	__asm__ __volatile__ ("pushfl\n"
+			      "popl %0\n"
+			      : "=r"(eflags));
+
+	/* Check Interrupt Enable flag */
+	return !!(eflags & 0x200);
+}
+
 inline int in_interrupt_context(void)
 {
 	return !!__in_isr;
diff --git a/core/nds32/task.c b/core/nds32/task.c
index 9969db34bc..edacb7975e 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -224,6 +224,16 @@ void __ram_code interrupt_enable(void)
 	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
+inline int is_interrupt_enabled(void)
+{
+	uint32_t val = 0;
+
+	asm volatile ("mfsr %0, $INT_MASK" : "=r"(val));
+
+	/* Interrupts are enabled if any of HW2 ~ HW15 is enabled */
+	return !!(val & 0xFFFC);
+}
+
 inline int in_interrupt_context(void)
 {
 	/* check INTL (Interrupt Stack Level) bits */
diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c
index cb9532f6dd..558177e969 100644
--- a/core/riscv-rv32i/task.c
+++ b/core/riscv-rv32i/task.c
@@ -199,6 +199,16 @@ void __ram_code interrupt_enable(void)
 	asm volatile ("csrs  mie, t0");
 }
 
+inline int is_interrupt_enabled(void)
+{
+	int mie = 0;
+
+	asm volatile ("csrr %0, mie" : "=r"(mie));
+
+	/* Check if MEIE bit is set in MIE register */
+	return !!(mie & 0x800);
+}
+
 inline int in_interrupt_context(void)
 {
 	return in_interrupt;