diff options
| author | Andrew McRae <amcrae@google.com> | 2020-05-23 13:53:58 +1000 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-05-27 03:14:03 +0000 |
| commit | 595c67985b07111cadc8ddc238ee1662870d7c0b (patch) | |
| tree | 4428541b84d4c3508999f36b2f1c7b712076f0e5 /core | |
| parent | d47f66468e4f84fbc3c56cd2f82611190e8dc093 (diff) | |
| download | chrome-ec-595c67985b07111cadc8ddc238ee1662870d7c0b.tar.gz | |
cortex-m: Init the MPU to check for correct operation
Disable all a MPU regions using the smallest supported size.
BUG=chromium:1085868
TEST=Boot successfully on Puff
TEST=Boot successfully on Volteer
BRANCH=none
Change-Id: Ie6924c3d9691ba6f4b218c9897b4e42b35b12bb7
Signed-off-by: Andrew McRae <amcrae@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2212010
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/include/mpu.h | 10 | ||||
| -rw-r--r-- | core/cortex-m/mpu.c | 17 |
2 files changed, 25 insertions, 2 deletions
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h index 17539fa09e..81aefa6a75 100644 --- a/core/cortex-m/include/mpu.h +++ b/core/cortex-m/include/mpu.h @@ -12,6 +12,11 @@ #include "config.h" /* chips might override MPU attribute settings */ /* + * ARMv7-M SRAM region + */ +#define CORTEX_M_SRAM_BASE 0x20000000 + +/* * Region assignment. 7 as the highest, a higher index has a higher priority. * For example, using 7 for .iram.text allows us to mark entire RAM XN except * .iram.text, which is used for hibernation. @@ -54,6 +59,11 @@ enum mpu_region { #define MPU_CTRL_ENABLE BIT(0) /* + * Minimum region size is 32 bytes, 5 bits of address space + */ +#define MPU_SIZE_BITS_MIN 5 + +/* * XN (execute never) bit. It's bit 12 if accessed by halfword. * 0: XN off * 1: XN on diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c index 53fffaaaa5..e2a2a464e1 100644 --- a/core/cortex-m/mpu.c +++ b/core/cortex-m/mpu.c @@ -68,6 +68,9 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit, if (region >= mpu_num_regions()) return -EC_ERROR_INVAL; + if (size_bit < MPU_SIZE_BITS_MIN) + return -EC_ERROR_INVAL; + asm volatile("isb; dsb;"); MPU_NUMBER = region; @@ -341,9 +344,19 @@ int mpu_pre_init(void) return EC_ERROR_UNIMPLEMENTED; mpu_disable(); + for (i = 0; i < num_mpu_regions; ++i) { - rv = mpu_config_region(i, CONFIG_RAM_BASE, CONFIG_RAM_SIZE, 0, - 0); + /* + * Disable all regions. + * + * We use the smallest possible size (32 bytes), but it + * doesn't really matter since the regions are disabled. + * + * Use the fixed SRAM region base to ensure base is aligned + * to the region size. + */ + rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN, + 0, 0, 0); if (rv != EC_SUCCESS) return rv; } |