diff options
| author | Yilun Lin <yllin@google.com> | 2019-03-18 16:36:48 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-27 05:57:29 -0700 |
| commit | 4a2a450ca48278b9f701461799df54faa6c4c395 (patch) | |
| tree | fa9a65559f4ba47a45d146bbada669c567fea0d5 /core | |
| parent | 6a144d98d3d09c2beea3ae5002a371a4f71a23f0 (diff) | |
| download | chrome-ec-4a2a450ca48278b9f701461799df54faa6c4c395.tar.gz | |
mt_scp: Support ROM section on internal SRAM.
Currently, kukui_scp's memory layout interleaves with RO and RW
sections. This complicates the MPU region configuration, and it
even unconfigurable.
This CL propose to simplify the layout and configuration by introducing
an IROM region, and re-layout the memory.
New layout would be:
---------------------------- 0x0
RO| .stepping_stone
| .text .rodata .data LMA
---------------------------- 0x100000
RW| .bss .data stack
| ipi shared buffer
---------------------------- 0x7C0000
BRANCH=None
BUG=b:123269246
TEST=1. w/o this CL: make buildall -j; mv build build.old
2. w/ this CL: make buildall -j;
3. compare smap by: ls build/*/*/ec.*.smap | \
sed -e 's|build/||' | \
xargs -I{} diff build/{} build.old/{}
and sees that only kukui_scp's smap changed.
Change-Id: I875a28c6b325ba66afe0387d3ea244190ddccde8
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1530263
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 24 |
1 files changed, 4 insertions, 20 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index 8a20fe931a..bb6b5ed84a 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -25,7 +25,7 @@ ENTRY(reset) MEMORY { #if !defined(CONFIG_FLASH_PHYSICAL) - IRAM (rwx) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE + IROM (rx) : ORIGIN = CONFIG_ROM_BASE, LENGTH = CONFIG_ROM_SIZE #else #if defined(SECTION_IS_RO) && defined(NPCX_RO_HEADER) /* @@ -43,8 +43,8 @@ MEMORY #ifdef CONFIG_SHAREDLIB SHARED_LIB (rx) : ORIGIN = FW_OFF(SHAREDLIB), LENGTH = FW_SIZE(SHAREDLIB) #endif - IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE #endif /* !CONFIG_FLASH_PHYSICAL */ + IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE #ifdef CONFIG_EXTERNAL_STORAGE #ifdef CONFIG_REPLACE_LOADER_WITH_BSS_SLOW @@ -120,7 +120,7 @@ SECTIONS } > CDRAM AT > FLASH #else #if !defined(CONFIG_FLASH_PHYSICAL) - } > IRAM + } > IROM #else } > FLASH #endif /* !CONFIG_FLASH_PHYSICAL */ @@ -265,7 +265,7 @@ SECTIONS #endif . = ALIGN(4); #if !defined(CONFIG_FLASH_PHYSICAL) - } > IRAM + } > IROM #elif defined(CONFIG_EXTERNAL_STORAGE) } > CDRAM AT > FLASH #else @@ -274,23 +274,7 @@ SECTIONS __data_lma_start = .; -#if !defined(CONFIG_FLASH_PHYSICAL) - /* - * Make a space for .data section's LMA. Otherwise, ld won't preserve - * a space for .data if .rodata and .bss sections are both in IRAM. - */ -#if defined(__clang__) - /* - * The lazy evaluation timing of symbols and builtin functions of ld and - * lld are different. - */ - .bss __data_lma_start + SIZEOF(.data) : { -#else - .bss __data_lma_start + __data_end - __data_start : { -#endif /* __clang__ */ -#else .bss : { -#endif /* !CONFIG_FLASH_PHYSICAL */ /* * Align to 512 bytes. This is convenient when some memory block * needs big alignment. This is the beginning of the RAM, so there |