common: replace 1 << digits, with BIT(digits)

Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.

Fix an error in motion_lid try to set bit 31 of a signed integer.

BUG=None
BRANCH=None
TEST=compile

Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

9 files changed, 32 insertions, 30 deletions

diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index 87e0631787..21de5bebf4 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -9,15 +9,16 @@
 #define __CROS_EC_CPU_H
 
 #include <stdint.h>
+#include "compile_time_macros.h"
 
 /* Macro to access 32-bit registers */
 #define CPUREG(addr) (*(volatile uint32_t*)(addr))
 
 #define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              (1 << 0)
-#define ST_TICKINT             (1 << 1)
-#define ST_CLKSOURCE           (1 << 2)
-#define ST_COUNTFLAG           (1 << 16)
+#define ST_ENABLE              BIT(0)
+#define ST_TICKINT             BIT(1)
+#define ST_CLKSOURCE           BIT(2)
+#define ST_COUNTFLAG           BIT(16)
 
 /* Nested Vectored Interrupt Controller */
 #define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
@@ -38,21 +39,21 @@
 #define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
 
 enum {
-	CPU_NVIC_MMFS_BFARVALID		= 1 << 15,
-	CPU_NVIC_MMFS_MFARVALID		= 1 << 7,
+	CPU_NVIC_MMFS_BFARVALID		= BIT(15),
+	CPU_NVIC_MMFS_MFARVALID		= BIT(7),
 
-	CPU_NVIC_CCR_ICACHE		= 1 << 17,
-	CPU_NVIC_CCR_DCACHE		= 1 << 16,
-	CPU_NVIC_CCR_DIV_0_TRAP		= 1 << 4,
-	CPU_NVIC_CCR_UNALIGN_TRAP	= 1 << 3,
+	CPU_NVIC_CCR_ICACHE		= BIT(17),
+	CPU_NVIC_CCR_DCACHE		= BIT(16),
+	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
+	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
 
 	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= 1 << 30,
-	CPU_NVIC_HFSR_VECTTBL		= 1 << 1,
+	CPU_NVIC_HFSR_FORCED		= BIT(30),
+	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
 
-	CPU_NVIC_SHCSR_MEMFAULTENA	= 1 << 16,
-	CPU_NVIC_SHCSR_BUSFAULTENA	= 1 << 17,
-	CPU_NVIC_SHCSR_USGFAULTENA	= 1 << 18,
+	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
+	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
+	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
 };
 
 /* System Control Block: cache registers */
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h
index 2dcf8be660..84a82bb3f8 100644
--- a/core/cortex-m/include/mpu.h
+++ b/core/cortex-m/include/mpu.h
@@ -45,16 +45,16 @@ enum mpu_region {
 #define MPU_TYPE_UNIFIED_MASK	0x00FF0001
 #define MPU_TYPE_REG_COUNT(t)	(((t) >> 8) & 0xFF)
 
-#define MPU_CTRL_PRIVDEFEN	(1 << 2)
-#define MPU_CTRL_HFNMIENA	(1 << 1)
-#define MPU_CTRL_ENABLE		(1 << 0)
+#define MPU_CTRL_PRIVDEFEN	BIT(2)
+#define MPU_CTRL_HFNMIENA	BIT(1)
+#define MPU_CTRL_ENABLE		BIT(0)
 
 /*
  * XN (execute never) bit. It's bit 12 if accessed by halfword.
  *   0: XN off
  *   1: XN on
  */
-#define MPU_ATTR_XN		(1 << 12)
+#define MPU_ATTR_XN		BIT(12)
 
 /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
 #define MPU_ATTR_NO_NO (0 << 8)  /* previleged no access, unprev no access */
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c
index 7daedbf7ab..f5a8f23c5c 100644
--- a/core/cortex-m/panic.c
+++ b/core/cortex-m/panic.c
@@ -199,13 +199,13 @@ static uint32_t get_exception_frame_size(const struct panic_data *pdata)
 
 	/* CPU uses xPSR[9] to indicate whether it padded the stack for
 	 * alignment or not. */
-	if (pdata->cm.frame[7] & (1 << 9))
+	if (pdata->cm.frame[7] & BIT(9))
 		frame_size += sizeof(uint32_t);
 
 #ifdef CONFIG_FPU
 	/* CPU uses EXC_RETURN[4] to indicate whether it stored extended
 	 * frame for FPU or not. */
-	if (!(pdata->cm.regs[11] & (1 << 4)))
+	if (!(pdata->cm.regs[11] & BIT(4)))
 		frame_size += 18 * sizeof(uint32_t);
 #endif
 
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index ef579339d1..5ab3272141 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -142,8 +142,8 @@ static const struct {
 static task_ tasks[TASK_ID_COUNT];
 
 /* Reset constants and state for all tasks */
-#define TASK_RESET_SUPPORTED		(1 << 31)
-#define TASK_RESET_LOCK			(1 << 30)
+#define TASK_RESET_SUPPORTED		BIT(31)
+#define TASK_RESET_LOCK			BIT(30)
 #define TASK_RESET_STATE_MASK		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
 #define TASK_RESET_WAITERS_MASK		~TASK_RESET_STATE_MASK
 #define TASK_RESET_UNSUPPORTED		0
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
index 8df6fa5d27..f4f8e424df 100644
--- a/core/cortex-m0/cpu.h
+++ b/core/cortex-m0/cpu.h
@@ -9,6 +9,7 @@
 #define __CROS_EC_CPU_H
 
 #include <stdint.h>
+#include "compile_time_macros.h"
 
 /* Macro to access 32-bit registers */
 #define CPUREG(addr) (*(volatile uint32_t*)(addr))
@@ -31,7 +32,7 @@
 #define CPU_NVIC_SHCSR2        CPUREG(0xe000ed1c)
 #define CPU_NVIC_SHCSR3        CPUREG(0xe000ed20)
 
-#define CPU_NVIC_CCR_UNALIGN_TRAP (1 << 3)
+#define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index 32dabcaf19..9b3f8ce0ed 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -371,7 +371,7 @@ uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
 			 * Trigger the scheduler when there's
 			 * no other irqs happening.
 			 */
-			CPU_SCB_ICSR = (1 << 28);
+			CPU_SCB_ICSR = BIT(28);
 		}
 	} else {
 		if (wait) {
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
index f5e4353cc3..f81bbbdc03 100644
--- a/core/nds32/cpu.h
+++ b/core/nds32/cpu.h
@@ -11,7 +11,7 @@
 #include <stdint.h>
 
 /* Process Status Word bits */
-#define PSW_GIE		(1 << 0) /* Global Interrupt Enable */
+#define PSW_GIE		BIT(0) /* Global Interrupt Enable */
 #define PSW_INTL_SHIFT	1        /* Interrupt Stack Level */
 #define PSW_INTL_MASK	(0x3 << PSW_INTL_SHIFT)
 
diff --git a/core/nds32/panic.c b/core/nds32/panic.c
index 4c855b5c06..3dabc1d2f0 100644
--- a/core/nds32/panic.c
+++ b/core/nds32/panic.c
@@ -174,7 +174,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 		panic_printf("Exception type: General exception [%s]\n",
 			itype_exc_type[(itype & 0xf)]);
 		panic_printf("Exception is caused by %s\n",
-			itype_inst[(itype & (1 << 4))]);
+			itype_inst[(itype & BIT(4))]);
 	}
 #endif
 }
diff --git a/core/nds32/task.c b/core/nds32/task.c
index f713c52442..7cd9049733 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -214,7 +214,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 void __ram_code interrupt_disable(void)
 {
 	/* Mask all interrupts, only keep division by zero exception */
-	uint32_t val = (1 << 30);
+	uint32_t val = BIT(30);
 	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
 	asm volatile ("dsb");
 }
@@ -222,7 +222,7 @@ void __ram_code interrupt_disable(void)
 void __ram_code interrupt_enable(void)
 {
 	/* Enable HW2 ~ HW15 and division by zero exception interrupts */
-	uint32_t val = ((1 << 30) | 0xFFFC);
+	uint32_t val = (BIT(30) | 0xFFFC);
 	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
@@ -600,7 +600,7 @@ static void ivic_init_irqs(void)
 	 * bit0 @ INT_CTRL = 0,
 	 * Interrupts still keep programmable priority level.
 	 */
-	set_int_ctrl((get_int_ctrl() & ~(1 << 0)));
+	set_int_ctrl((get_int_ctrl() & ~BIT(0)));
 
 	/*
 	 * Re-enable global interrupts in case they're disabled.  On a reboot,