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| author | Ruibin Chang <Ruibin.Chang@ite.com.tw> | 2019-11-12 14:31:48 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-22 11:22:02 +0000 |
| commit | 85b276f5158a544229073f24834147bb2ae5ebb8 (patch) | |
| tree | a3a9565fc311841d8872ca26e5daeb15cd62971e /core | |
| parent | 62c28034b339011cb877feca705dfeb6b695459e (diff) | |
| download | chrome-ec-85b276f5158a544229073f24834147bb2ae5ebb8.tar.gz | |
chip/it8xxx1, chip/it8xxx2: GPIO, WUC and IRQ for chip it83201/it83202
GPIO, WUC and IRQ changes for chip it83201/it83202.
BRANCH=None
BUG=b:133460224
TEST=test GPIO group O, P, Q, R
1.Input: external input 3.3v, GPDR of corresponding pin is 1.
(GCR31, GCR32 select 1.8v, validate again for O and
P group)
2.Output: GPDR of corresponding pin set 1, measure 3.3v.
3.INT: GPIO_INT input trigger => WU INT (select high, low,
rising, falling, both edge trigger mode) => INT => CPU INT
4.Test power-up and down with this CL on ampton.
Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core')
0 files changed, 0 insertions, 0 deletions