it83xx: read_clear_int_mask() read and clear interrupt bit.

This change pulled the operation of interrupt disable into
read_clear_int_mask().
Because riscv core supports instruction csrrc to atomic read and
clear bit in CSR register. With this change, we won't need to separate
operations of reading and clearing interrupt bit on riscv core.

BUG=none
BRANCH=none
TEST=read_clear_int_mask() is able to disable interrupt and return
     saved interrupt bit on both nds32 and riscv cores.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739
Reviewed-by: Jett Rink <jettrink@chromium.org>

3 files changed, 31 insertions, 26 deletions

diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h
index 8928fe3373..792093d598 100644
--- a/core/nds32/atomic.h
+++ b/core/nds32/atomic.h
@@ -14,32 +14,32 @@
 
 static inline void atomic_clear(uint32_t volatile *addr, uint32_t bits)
 {
-	uint32_t int_mask = get_int_mask();
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	*addr &= ~bits;
 	set_int_mask(int_mask);
 }
 
 static inline void atomic_or(uint32_t volatile *addr, uint32_t bits)
 {
-	uint32_t int_mask = get_int_mask();
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	*addr |= bits;
 	set_int_mask(int_mask);
 }
 
 static inline void atomic_add(uint32_t volatile *addr, uint32_t value)
 {
-	uint32_t int_mask = get_int_mask();
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	*addr += value;
 	set_int_mask(int_mask);
 }
 
 static inline void atomic_sub(uint32_t volatile *addr, uint32_t value)
 {
-	uint32_t int_mask = get_int_mask();
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	*addr -= value;
 	set_int_mask(int_mask);
 }
@@ -47,8 +47,8 @@ static inline void atomic_sub(uint32_t volatile *addr, uint32_t value)
 static inline uint32_t atomic_read_clear(uint32_t volatile *addr)
 {
 	uint32_t val;
-	uint32_t int_mask = get_int_mask();
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	val = *addr;
 	*addr = 0;
 	set_int_mask(int_mask);
diff --git a/core/nds32/task.c b/core/nds32/task.c
index f034c53f48..21bd8d5edd 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -473,11 +473,18 @@ uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
 	return events & event_mask;
 }
 
-uint32_t __ram_code get_int_mask(void)
+uint32_t __ram_code read_clear_int_mask(void)
 {
-	uint32_t ret;
-	asm volatile ("mfsr %0, $INT_MASK" : "=r"(ret));
-	return ret;
+	uint32_t int_mask, int_dis = BIT(30);
+
+	asm volatile(
+		"mfsr %0, $INT_MASK\n\t"
+		"mtsr %1, $INT_MASK\n\t"
+		"dsb\n\t"
+		: "=&r"(int_mask)
+		: "r"(int_dis));
+
+	return int_mask;
 }
 
 void __ram_code set_int_mask(uint32_t val)
@@ -526,18 +533,16 @@ void task_disable_task(task_id_t tskid)
 
 void __ram_code task_enable_irq(int irq)
 {
-	uint32_t int_mask = get_int_mask();
+	uint32_t int_mask = read_clear_int_mask();
 
-	interrupt_disable();
 	chip_enable_irq(irq);
 	set_int_mask(int_mask);
 }
 
 void __ram_code task_disable_irq(int irq)
 {
-	uint32_t int_mask = get_int_mask();
+	uint32_t int_mask = read_clear_int_mask();
 
-	interrupt_disable();
 	chip_disable_irq(irq);
 	set_int_mask(int_mask);
 }
diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c
index 1182aaac82..3ad78994bd 100644
--- a/core/riscv-rv32i/task.c
+++ b/core/riscv-rv32i/task.c
@@ -468,12 +468,14 @@ uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
 	return events & event_mask;
 }
 
-uint32_t __ram_code get_int_mask(void)
+uint32_t __ram_code read_clear_int_mask(void)
 {
-	uint32_t ret;
+	uint32_t mie, meie = BIT(11);
 
-	asm volatile ("csrr %0, mie" : "=r"(ret));
-	return ret;
+	/* Read and clear MEIE bit of MIE register. */
+	asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
+
+	return mie;
 }
 
 void __ram_code set_int_mask(uint32_t val)
@@ -504,18 +506,16 @@ void task_disable_task(task_id_t tskid)
 
 void __ram_code task_enable_irq(int irq)
 {
-	uint32_t int_mask = get_int_mask();
+	uint32_t int_mask = read_clear_int_mask();
 
-	interrupt_disable();
 	chip_enable_irq(irq);
 	set_int_mask(int_mask);
 }
 
 void __ram_code task_disable_irq(int irq)
 {
-	uint32_t int_mask = get_int_mask();
+	uint32_t int_mask = read_clear_int_mask();
 
-	interrupt_disable();
 	chip_disable_irq(irq);
 	set_int_mask(int_mask);
 }