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| author | Ian Chao <mlchao@nuvoton.com> | 2014-12-06 14:23:02 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-01-14 03:16:10 +0000 |
| commit | 4ee50837a0263a5bfcb61e32a862797ede387c78 (patch) | |
| tree | af86c4bd09ff9e4d364ff66444a26f9091b15d14 /core | |
| parent | 3951165fe9182cb6c9981d0a69c36765c7fe8916 (diff) | |
| download | chrome-ec-4ee50837a0263a5bfcb61e32a862797ede387c78.tar.gz | |
nuc: Add all IC specific drivers of NPCX5M5G
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index bd813a8b22..5d70f366e8 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -19,6 +19,9 @@ MEMORY { FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE +#ifdef CONFIG_CODERAM_ARCH + CDRAM (rx) : ORIGIN = CONFIG_CDRAM_BASE, LENGTH = CONFIG_CDRAM_SIZE +#endif #ifdef RSA_PUBLIC_KEY_SIZE PSTATE(r) : ORIGIN = FW_OFF(SECTION) + FW_SIZE(SECTION), \ LENGTH = CONFIG_FW_PSTATE_SIZE @@ -43,12 +46,21 @@ SECTIONS #endif OUTDIR/core/CORE/init.o (.text) *(.text*) +#ifdef CONFIG_CODERAM_ARCH + __flash_lpfw_start = .; + /* Entering deep idle FW for better power consumption */ + KEEP(*(.lowpower_ram)) + __flash_lpfw_end = .; + } > CDRAM AT > FLASH +#else #ifdef COMPILE_FOR_RAM } > IRAM #else } > FLASH #endif +#endif . = ALIGN(4); + .rodata : { /* Symbols defined here are declared in link_defs.h */ __irqprio = .; @@ -151,11 +163,15 @@ SECTIONS KEEP(*(.google)) #endif . = ALIGN(4); +#ifdef CONFIG_CODERAM_ARCH + } > CDRAM AT > FLASH +#else #ifdef COMPILE_FOR_RAM } > IRAM #else } > FLASH #endif +#endif __ro_end = . ; __deferred_funcs_count = @@ -184,8 +200,13 @@ SECTIONS #ifdef COMPILE_FOR_RAM .data : { #else +#ifdef CONFIG_CODERAM_ARCH + __data_start = . ; + .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)) { +#else .data : AT(ADDR(.rodata) + SIZEOF(.rodata)) { #endif +#endif . = ALIGN(4); __data_start = .; *(.data.tasks) |