diff options
| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2020-06-03 16:48:40 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-04 10:27:44 +0000 |
| commit | f1f7872295a508c4a4c9aad6e1640556466ff7a7 (patch) | |
| tree | 3200bb205a0b26953c636ba5526cb219ce7dadbf /core | |
| parent | b7da665db8e7a731ad4d3839424c6d42016016ea (diff) | |
| download | chrome-ec-f1f7872295a508c4a4c9aad6e1640556466ff7a7.tar.gz | |
core/riscv-rv32i: add error handling for chip_get_ec_int()
chip_get_ec_int() returns -1 if it cannot find the corresponding
interrupt source.
BRANCH=none
BUG=b:146213943
BUG=b:157521370
TEST=1. make BOARD=asurada
2. flash_ec --board=asurada --image build/asurada/ec.bin
3. (EC console)> version
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I5021ed80f50a99b15d9b9a90a9181077f63bd4be
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227777
Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/riscv-rv32i/init.S | 20 | ||||
| -rw-r--r-- | core/riscv-rv32i/task.c | 11 |
2 files changed, 21 insertions, 10 deletions
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S index 844a49d7c3..2fc47d34d4 100644 --- a/core/riscv-rv32i/init.S +++ b/core/riscv-rv32i/init.S @@ -184,6 +184,8 @@ __sp_16byte_aligned: j unhandled_interrupt __irq_handler: jal start_irq_handler + /* t0 = -1 if it cannot find the corresponding interrupt source */ + bltz t0, unhandled_interrupt /* get EC interrupt group 0-15 or 16:ecall */ la t0, ec_int_group /* get corresponding isr */ @@ -268,10 +270,10 @@ __reset: #else csrw mstatus, zero #endif - /* - * move content of return address(ra) into t5 and then store the content - * into variable "ec_reset_lp" later after memory initialization. - */ + /* + * move content of return address(ra) into t5 and then store the content + * into variable "ec_reset_lp" later after memory initialization. + */ mv t5, ra /* Clear the link register */ li ra, 0 @@ -314,8 +316,8 @@ data_loop: la t0, ec_reset_lp sw t5, 0(t0) #ifdef CHIP_FAMILY_IT8XXX2 - /* clear BRAM if it is not valid */ - jal chip_bram_valid + /* clear BRAM if it is not valid */ + jal chip_bram_valid #endif /* Jump to C routine */ jal main @@ -385,9 +387,9 @@ excep_handler: csrr sp, mscratch sw sp, 30*4(a0) /* put a sane stack pointer */ - la sp, stack_end - /* jump to panic dump C routine */ - jal report_panic + la sp, stack_end + /* jump to panic dump C routine */ + jal report_panic j . .align 2 diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c index 4bd2c44a03..e4feb30eb6 100644 --- a/core/riscv-rv32i/task.c +++ b/core/riscv-rv32i/task.c @@ -326,8 +326,13 @@ void __ram_code start_irq_handler(void) ec_int = sw_int_num; ec_int_group = 16; } else { - /* Determine interrupt number */ + /* + * Determine interrupt number. + * -1 if it cannot find the corresponding interrupt source. + */ ec_int = chip_get_ec_int(); + if (ec_int == -1) + goto error; ec_int_group = chip_get_intc_group(ec_int); } @@ -345,6 +350,10 @@ void __ram_code start_irq_handler(void) irq_dist[ec_int]++; #endif +error: + /* cannot use return statement because a0 has been used */ + asm volatile ("add t0, zero, %0" :: "r"(ec_int)); + /* restore a0, a1, and a2 */ asm volatile ("lw a0, 0(sp)"); asm volatile ("lw a1, 1*4(sp)"); |