diff options
author | Dino Li <Dino.Li@ite.com.tw> | 2021-01-20 11:22:24 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-02-04 15:28:09 +0000 |
commit | 5a8e3770118786519a33fe9691163e3554570419 (patch) | |
tree | 0460dd8f0dac9a2bbfc6ecd251047c2b86ab2d98 /core | |
parent | 15d0d51ea65961f9eac40c774be7bb834f69cc19 (diff) | |
download | chrome-ec-5a8e3770118786519a33fe9691163e3554570419.tar.gz |
riscv-rv32i: store EC interrupt number in panic info
This change stores EC INT number in panic info (TP register)
if the number isn't valid.
For CPU interrupt and exception code, we can check mcause
register in panic info.
BUG=b:179206540
BRANCH=none
TEST=fire an invalid EC INT (eg, number 188) and checking panic
info to see if the number is stored in TP:
=== EXCEPTION: MCAUSE=8000000b ===
S11 00000000 S10 00000000 S9 00000000 S8 00000000
S7 00000000 S6 00000000 S5 ffe17b7f S4 fff0bdc0
S3 0000fffe S2 00000000 S1 00000000 S0 00000000
T6 00000000 T5 00000000 T4 00000058 T3 00000009
T2 00000000 T1 00000010 T0 00000800 A7 00000000
A6 00000001 A5 80026860 A4 ffffffff A3 00000008
A2 80109be8 A1 00000000 A0 0000f304 TP bad000bc
GP 80103930 RA 80000f2c SP 80106bb8 MEPC 80000dee
Exception type: Environment call from M-mode
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: If4ead38266d1c5b3453d5dd5e5f65de5af793f57
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2638998
Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'core')
-rw-r--r-- | core/riscv-rv32i/init.S | 21 | ||||
-rw-r--r-- | core/riscv-rv32i/task.c | 29 |
2 files changed, 26 insertions, 24 deletions
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S index 0bc99052da..eee72503d3 100644 --- a/core/riscv-rv32i/init.S +++ b/core/riscv-rv32i/init.S @@ -183,9 +183,19 @@ __sp_16byte_aligned: /* This interrupt is unhandled */ j unhandled_interrupt __irq_handler: + /* save a0, a1, and a2 for syscall */ + addi sp, sp, -4*3 + sw a0, 0(sp) + sw a1, 1*4(sp) + sw a2, 2*4(sp) jal start_irq_handler - /* t0 = -1 if it cannot find the corresponding interrupt source */ - bltz t0, unhandled_interrupt + /* a0 = -1 if it cannot find the corresponding interrupt source */ + bltz a0, unhandled_interrupt + /* restore a0, a1, and a2 */ + lw a0, 0(sp) + lw a1, 1*4(sp) + lw a2, 2*4(sp) + addi sp, sp, 4*3 /* get EC interrupt group 0-15 or 16:ecall */ la t0, ec_int_group /* get corresponding isr */ @@ -332,10 +342,11 @@ unhandled_ec_irq: unhandled_interrupt: li tp, 0xBAD0 __unhandled_irq: - slli tp, tp, 8 - csrr t0, mcause + slli tp, tp, 16 + la t0, ec_int + lw t0, 0(t0) add tp, tp, t0 - j excep_handler /* display exception with TP 80bad[0|1]<irq> */ + j excep_handler /* display exception with TP bad[0|1]<ec_int> */ .global excep_handler excep_handler: diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c index ae1609e9a2..58a5e06ba3 100644 --- a/core/riscv-rv32i/task.c +++ b/core/riscv-rv32i/task.c @@ -311,14 +311,14 @@ void __ram_code update_exc_start_time(void) #endif } -void __ram_code start_irq_handler(void) +/** + * The beginning of interrupt handler of c language code. + * + * @param none + * @return -1 if it cannot find the corresponding interrupt source. + */ +int __ram_code start_irq_handler(void) { - /* save a0, a1, and a2 for syscall */ - asm volatile ("addi sp, sp, -4*3"); - asm volatile ("sw a0, 0(sp)"); - asm volatile ("sw a1, 1*4(sp)"); - asm volatile ("sw a2, 2*4(sp)"); - in_interrupt = 1; /* If this is a SW interrupt */ @@ -330,9 +330,8 @@ void __ram_code start_irq_handler(void) * Determine interrupt number. * -1 if it cannot find the corresponding interrupt source. */ - ec_int = chip_get_ec_int(); - if (ec_int == -1) - goto error; + if (chip_get_ec_int() == -1) + return -1; ec_int_group = chip_get_intc_group(ec_int); } @@ -350,15 +349,7 @@ void __ram_code start_irq_handler(void) irq_dist[ec_int]++; #endif -error: - /* cannot use return statement because a0 has been used */ - asm volatile ("add t0, zero, %0" :: "r"(ec_int)); - - /* restore a0, a1, and a2 */ - asm volatile ("lw a0, 0(sp)"); - asm volatile ("lw a1, 1*4(sp)"); - asm volatile ("lw a2, 2*4(sp)"); - asm volatile ("addi sp, sp, 4*3"); + return EC_SUCCESS; } void __ram_code end_irq_handler(void) |