core/cortex-m/mpu.c: Format with clang-format

BUG=b:236386294
BRANCH=none
TEST=none

Change-Id: Ia2f95d269b42a5dac2639c3a25606808843a50f1
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729823
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>

1 files changed, 26 insertions, 35 deletions

diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
index 29da931a28..ec9ceca201 100644
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -37,7 +37,6 @@ bool mpu_is_unified(void)
 	return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0;
 }
 
-
 /**
  * Update a memory region.
  *
@@ -74,7 +73,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 	asm volatile("isb; dsb;");
 
 	MPU_NUMBER = region;
-	MPU_SIZE &= ~1;					/* Disable */
+	MPU_SIZE &= ~1; /* Disable */
 	if (enable) {
 		MPU_BASE = addr;
 		/*
@@ -85,8 +84,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 		 * according to the doc, but they don't ..., do a single 32-bit
 		 * one.
 		 */
-		REG32(&MPU_SIZE) = ((uint32_t)attr << 16)
-				 | (srd << 8) | ((size_bit - 1) << 1) | 1;
+		REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) |
+				   ((size_bit - 1) << 1) | 1;
 	}
 
 	asm volatile("isb; dsb;");
@@ -117,7 +116,7 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
 	 * regions must be naturally aligned to their size.
 	 */
 	uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr),
-				     alignment_log2(size));
+					alignment_log2(size));
 	uint8_t subregion_disable = 0;
 
 	if (natural_alignment >= 5) {
@@ -159,10 +158,9 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
 		*consumed = 1 << natural_alignment;
 	}
 
-	return mpu_update_region(region,
-			       addr & ~((1 << natural_alignment) - 1),
-			       natural_alignment,
-			       attr, enable, subregion_disable);
+	return mpu_update_region(region, addr & ~((1 << natural_alignment) - 1),
+				 natural_alignment, attr, enable,
+				 subregion_disable);
 }
 
 /**
@@ -188,8 +186,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 	if (size == 0)
 		return EC_SUCCESS;
 
-	rv = mpu_config_region_greedy(region, addr, size,
-				      attr, enable, &consumed);
+	rv = mpu_config_region_greedy(region, addr, size, attr, enable,
+				      &consumed);
 	if (rv != EC_SUCCESS)
 		return rv;
 	ASSERT(consumed <= size);
@@ -198,8 +196,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 
 	/* Regions other than DATA_RAM_TEXT may use two MPU regions */
 	if (size > 0 && region != REGION_DATA_RAM_TEXT) {
-		rv = mpu_config_region_greedy(region + 1, addr, size,
-					      attr, enable, &consumed);
+		rv = mpu_config_region_greedy(region + 1, addr, size, attr,
+					      enable, &consumed);
 		if (rv != EC_SUCCESS)
 			return rv;
 		ASSERT(consumed <= size);
@@ -223,8 +221,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size,
 			     uint8_t texscb)
 {
-	return mpu_config_region(region, addr, size,
-				 MPU_ATTR_RW_RW | texscb, 1);
+	return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb,
+				 1);
 }
 
 void mpu_enable(void)
@@ -247,13 +245,9 @@ int mpu_protect_data_ram(void)
 	int ret;
 
 	/* Prevent code execution from data RAM */
-	ret = mpu_config_region(REGION_DATA_RAM,
-				CONFIG_RAM_BASE,
-				CONFIG_DATA_RAM_SIZE,
-				MPU_ATTR_XN |
-				MPU_ATTR_RW_RW |
-				MPU_ATTR_INTERNAL_SRAM,
-				1);
+	ret = mpu_config_region(
+		REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -271,18 +265,16 @@ int mpu_protect_code_ram(void)
 	return mpu_config_region(REGION_STORAGE,
 				 CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF,
 				 CONFIG_CODE_RAM_SIZE,
-				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM,
-				 1);
+				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1);
 }
 #else
 int mpu_lock_ro_flash(void)
 {
 	/* Prevent execution from internal mapped RO flash */
-	return mpu_config_region(REGION_STORAGE,
-				 CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
-				 CONFIG_RO_SIZE,
-				 MPU_ATTR_XN | MPU_ATTR_RW_RW |
-				 MPU_ATTR_FLASH_MEMORY, 1);
+	return mpu_config_region(
+		REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
+		CONFIG_RO_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1);
 }
 
 /* Represent RW with at most 2 MPU regions. */
@@ -298,8 +290,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void)
 	 * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the
 	 * address used for an MPU region must be aligned to the size.
 	 */
-	aligned_size_bit =
-		__fls(regions.addr[0] & -regions.addr[0]);
+	aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]);
 	regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE);
 	regions.addr[1] = regions.addr[0] + regions.size[0];
 	regions.size[1] = CONFIG_RW_SIZE - regions.size[0];
@@ -386,10 +377,10 @@ int mpu_lock_rollback(int lock)
 
 #ifdef CONFIG_CHIP_UNCACHED_REGION
 /* Store temporarily the regions ranges to use them for the MPU configuration */
-#define REGION(_name, _flag, _start, _size) \
-	static const uint32_t CONCAT2(_region_start_, _name) \
+#define REGION(_name, _flag, _start, _size)                           \
+	static const uint32_t CONCAT2(_region_start_, _name)          \
 		__attribute__((unused, section(".unused"))) = _start; \
-	static const uint32_t CONCAT2(_region_size_, _name) \
+	static const uint32_t CONCAT2(_region_size_, _name)           \
 		__attribute__((unused, section(".unused"))) = _size;
 #include "memory_regions.inc"
 #undef REGION
@@ -424,7 +415,7 @@ int mpu_pre_init(void)
 		 * to the region size.
 		 */
 		rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN,
-			0, 0, 0);
+				       0, 0, 0);
 		if (rv != EC_SUCCESS)
 			return rv;
 	}