diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2012-06-15 15:58:23 +0000 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2012-06-15 13:18:40 -0700 |
| commit | b4d996a5ea2cfeb8358a83bc1698a23b819e9242 (patch) | |
| tree | ce4b9253eb74fc0eab0c7a09a594f3a9952ec42f /core | |
| parent | cca78cfcfdda7700dc3e5659ef68cadedaef136b (diff) | |
| download | chrome-ec-b4d996a5ea2cfeb8358a83bc1698a23b819e9242.tar.gz | |
Move System Control Block registers to core header
The SCB registers are defined in the ARMv7-M architecture, so they are
common to all chips.
We will need System Control Register (SCR aka SYSCTRL) to implement
power management on stm32.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=snow
Change-Id: I35c283731306541b3d21398c96fdca89954fe20a
Reviewed-on: https://gerrit.chromium.org/gerrit/25392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index bd94e179fe..7e032164a7 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -21,4 +21,6 @@ #define CPU_NVIC_APINT CPUREG(0xe000ed0c) #define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) +#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) + #endif /* __CPU_H */ |