diff options
| author | Diana Z <dzigterman@chromium.org> | 2020-11-03 14:58:57 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-11-05 01:28:40 +0000 |
| commit | e609f07eef8b851b19bf4b59b5263ac702d8b871 (patch) | |
| tree | 2211fbef28040cfbc9ce9831b310524c1e06ec72 /core | |
| parent | 899412aaf662619fbf66bbdc0398c7d69aebc482 (diff) | |
| download | chrome-ec-e609f07eef8b851b19bf4b59b5263ac702d8b871.tar.gz | |
COIL: Rename CONFIG_I2C_PERIPHERAL
Rename CONFIG_I2C_PERIPHERAL and related comments.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I3f148e976f3a4d6a1dc6c58686368c056290d5d4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/nds32/ec.lds.S | 6 | ||||
| -rw-r--r-- | core/riscv-rv32i/ec.lds.S | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 98edb36c3f..4565600b05 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -22,7 +22,7 @@ MEMORY { FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE -#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE) +#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL) H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE #endif } @@ -292,13 +292,13 @@ SECTIONS __config_ec_writable_storage_size = CONFIG_EC_WRITABLE_STORAGE_SIZE; #endif -#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE) +#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL) .h2ram (NOLOAD) : { . += CONFIG_H2RAM_HOST_LPC_IO_BASE; *(.h2ram.pool.hostcmd) . = ALIGN(256); *(.h2ram.pool.acpiec) -#ifdef CONFIG_I2C_SLAVE +#ifdef CONFIG_I2C_PERIPHERAL . = ALIGN(256); *(.h2ram.pool.i2cslv) #endif diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index 15a26e5eff..1a979ddcaa 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -41,7 +41,7 @@ MEMORY */ ILM (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) -#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE) +#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL) H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE #endif #else @@ -341,13 +341,13 @@ SECTIONS #endif #if defined(CHIP_FAMILY_IT8XXX2) -#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE) +#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_PERIPHERAL) .h2ram (NOLOAD) : { . += CONFIG_H2RAM_HOST_LPC_IO_BASE; *(.h2ram.pool.hostcmd) . = ALIGN(256); *(.h2ram.pool.acpiec) -#ifdef CONFIG_I2C_SLAVE +#ifdef CONFIG_I2C_PERIPHERAL . = ALIGN(256); *(.h2ram.pool.i2cslv) #endif |