cts: Added GPIO test suite

Contains code for all the gpio tests so far. Code in
cts_task for th and dut is for testing purposes and
test result reporting will be updated in the next
patch.

BRANCH=None
BUG=None
TEST=Manual
- Connect handshake and gpio test lines between th and dut
- Build tests
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /def/ttyACM1' in another
- Flash boards
- All test results should print either passed or unknown

Change-Id: I7142fb87a6ce0a20c571cde608fbbe60e35898ea
Reviewed-on: https://chromium-review.googlesource.com/359935
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

1 files changed, 21 insertions, 0 deletions

diff --git a/cts/gpio/gpio_common.h b/cts/gpio/gpio_common.h
new file mode 100644
index 0000000000..b19d23165a
--- /dev/null
+++ b/cts/gpio/gpio_common.h
@@ -0,0 +1,21 @@
+/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __GPIO_COMMON_H
+#define __GPIO_COMMON_H
+
+/* sync_test tests whether sync completes successfully
+ * set_low_test checks if the dut can set a line low
+ * set_high test checks if the dut can set a line high
+ * read_low_test checks if the dut can read a line that is low
+ * read_high_test checks if the dut can read a line that is high
+ * od_read_high_test checks if the dut reads its true pin level (success)
+ * or its register level when configured as a low open drain output pin
+   */
+
+#define READ_WAIT_TIME_MS 100
+#define GPIO_CTS_TEST_COUNT 6
+
+#endif