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authorAlec Berg <alecaberg@chromium.org>2014-01-06 18:07:27 -0800
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-02-22 00:48:25 +0000
commit9305b84ab2a844393b90b897c394a557d8dfa8fb (patch)
tree1cd7fe0ebaccce6d909e736ced277a31090e2721 /driver/accel_kxcj9.h
parent8df483bf594d6251005a88de211078e2a445a55d (diff)
downloadchrome-ec-9305b84ab2a844393b90b897c394a557d8dfa8fb.tar.gz
rambi: Accelerometer driver for kxcj9.
Added accelerometer driver for kxcj9 accelerometers. Currently the accelerometers aren't being used by anything, but there are console commands, accelwrite and accelread, to perform transactions. BUG=none BRANCH=rambi TEST=Used EC console commands to test that accelerometers respond and data looks reasonable. Original-Change-Id: I6ddcf04ec278adeacb148c19b10c3c296b467954 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/184693 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 5e1d2052b034b2400b98b2126243e01397a2ce56) Conflicts: board/clapper/board.c board/clapper/board.h board/glimmer/board.c board/glimmer/board.h Change-Id: If8744ddc3273fc08e29830adfd068dc302dd120a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187432 Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'driver/accel_kxcj9.h')
-rw-r--r--driver/accel_kxcj9.h132
1 files changed, 132 insertions, 0 deletions
diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h
new file mode 100644
index 0000000000..9451421be5
--- /dev/null
+++ b/driver/accel_kxcj9.h
@@ -0,0 +1,132 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* KXCJ9 gsensor module for Chrome EC */
+
+#ifndef __CROS_EC_ACCEL_KXCJ9_H
+#define __CROS_EC_ACCEL_KXCJ9_H
+
+/*
+ * 7-bit address is 000111Xb. Where 'X' is determined
+ * by the voltage on the ADDR pin.
+ */
+#define KXCJ9_ADDR0 0x1c
+#define KXCJ9_ADDR1 0x1e
+
+/* Chip-specific registers */
+#define KXCJ9_XOUT_L 0x06
+#define KXCJ9_XOUT_H 0x07
+#define KXCJ9_YOUT_L 0x08
+#define KXCJ9_YOUT_H 0x09
+#define KXCJ9_ZOUT_L 0x0a
+#define KXCJ9_ZOUT_H 0x0b
+#define KXCJ9_DCST_RESP 0x0c
+#define KXCJ9_WHOAMI 0x0f
+#define KXCJ9_INT_SRC1 0x16
+#define KXCJ9_INT_SRC2 0x17
+#define KXCJ9_STATUS 0x18
+#define KXCJ9_INT_REL 0x1a
+#define KXCJ9_CTRL1 0x1b
+#define KXCJ9_CTRL2 0x1d
+#define KXCJ9_INT_CTRL1 0x1e
+#define KXCJ9_INT_CTRL2 0x1f
+#define KXCJ9_DATA_CTRL 0x21
+#define KXCJ9_WAKEUP_TIMER 0x29
+#define KXCJ9_SELF_TEST 0x3a
+#define KXCJ9_WAKEUP_THRESHOLD 0x6a
+
+#define KXCJ9_INT_SRC1_WUFS (1 << 1)
+#define KXCJ9_INT_SRC1_DRDY (1 << 4)
+
+#define KXCJ9_INT_SRC2_ZPWU (1 << 0)
+#define KXCJ9_INT_SRC2_ZNWU (1 << 1)
+#define KXCJ9_INT_SRC2_YPWU (1 << 2)
+#define KXCJ9_INT_SRC2_YNWU (1 << 3)
+#define KXCJ9_INT_SRC2_XPWU (1 << 4)
+#define KXCJ9_INT_SRC2_XNWU (1 << 5)
+
+#define KXCJ9_STATUS_INT (1 << 4)
+
+#define KXCJ9_CTRL1_WUFE (1 << 1)
+#define KXCJ9_CTRL1_DRDYE (1 << 5)
+#define KXCJ9_CTRL1_PC1 (1 << 7)
+
+#define KXCJ9_GSEL_2G (0 << 3)
+#define KXCJ9_GSEL_4G (1 << 3)
+#define KXCJ9_GSEL_8G (2 << 3)
+#define KXCJ9_GSEL_8G_14BIT (3 << 3)
+
+#define KXCJ9_RES_8BIT (0 << 6)
+#define KXCJ9_RES_12BIT (1 << 6)
+
+#define KXCJ9_CTRL2_OWUF (7 << 0)
+#define KXCJ9_CTRL2_DCST (1 << 4)
+#define KXCJ9_CTRL2_SRST (1 << 7)
+
+#define KXCJ9_OWUF_0_781HZ 0
+#define KXCJ9_OWUF_1_563HZ 1
+#define KXCJ9_OWUF_3_125HZ 2
+#define KXCJ9_OWUF_6_250HZ 3
+#define KXCJ9_OWUF_12_50HZ 4
+#define KXCJ9_OWUF_25_00HZ 5
+#define KXCJ9_OWUF_50_00HZ 6
+#define KXCJ9_OWUF_100_0HZ 7
+
+#define KXCJ9_INT_CTRL1_IEL (1 << 3)
+#define KXCJ9_INT_CTRL1_IEA (1 << 4)
+#define KXCJ9_INT_CTRL1_IEN (1 << 5)
+
+#define KXCJ9_INT_CTRL2_ZPWUE (1 << 0)
+#define KXCJ9_INT_CTRL2_ZNWUE (1 << 1)
+#define KXCJ9_INT_CTRL2_YPWUE (1 << 2)
+#define KXCJ9_INT_CTRL2_YNWUE (1 << 3)
+#define KXCJ9_INT_CTRL2_XPWUE (1 << 4)
+#define KXCJ9_INT_CTRL2_XNWUE (1 << 5)
+
+#define KXCJ9_OSA_0_781HZ 8
+#define KXCJ9_OSA_1_563HZ 9
+#define KXCJ9_OSA_3_125HZ 0xa
+#define KXCJ9_OSA_6_250HZ 0xb
+#define KXCJ9_OSA_12_50HZ 0
+#define KXCJ9_OSA_25_00HZ 1
+#define KXCJ9_OSA_50_00HZ 2
+#define KXCJ9_OSA_100_0HZ 3
+#define KXCJ9_OSA_200_0HZ 4
+#define KXCJ9_OSA_400_0HZ 5
+#define KXCJ9_OSA_800_0HZ 6
+#define KXCJ9_OSA_1600_HZ 7
+
+
+/**
+ * Write the accelerometer range.
+ *
+ * @param id Target accelerometer
+ * @param range Range (KXCJ9_GSEL_*).
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int accel_write_range(const enum accel_id id, const int range);
+
+/**
+ * Write the accelerometer resolution.
+ *
+ * @param id Target accelerometer
+ * @param range Resolution (KXCJ9_RES_*).
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int accel_write_resolution(const enum accel_id id, const int res);
+
+/**
+ * Write the accelerometer data rate.
+ *
+ * @param id Target accelerometer
+ * @param range Data rate (KXCJ9_OSA_*).
+ *
+ * @return EC_SUCCESS if successful, non-zero if error.
+ */
+int accel_write_datarate(const enum accel_id id, const int rate);
+
+#endif /* __CROS_EC_ACCEL_KXCJ9_H */