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| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /driver/accel_kxcj9.h | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-252457d4b21f46889eebad61d4c0a65331919cec.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'driver/accel_kxcj9.h')
| -rw-r--r-- | driver/accel_kxcj9.h | 111 |
1 files changed, 0 insertions, 111 deletions
diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h deleted file mode 100644 index f7488317f0..0000000000 --- a/driver/accel_kxcj9.h +++ /dev/null @@ -1,111 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* KXCJ9 gsensor module for Chrome EC */ - -#ifndef __CROS_EC_ACCEL_KXCJ9_H -#define __CROS_EC_ACCEL_KXCJ9_H - -#include "task.h" - -/* - * 7-bit address is 000111Xb. Where 'X' is determined - * by the voltage on the ADDR pin. - */ -#define KXCJ9_ADDR0_FLAGS 0x0E -#define KXCJ9_ADDR1_FLAGS 0x0D -#define KXCJ9_WHO_AM_I_VAL 0x0A - -/* Chip-specific registers */ -#define KXCJ9_XOUT_L 0x06 -#define KXCJ9_XOUT_H 0x07 -#define KXCJ9_YOUT_L 0x08 -#define KXCJ9_YOUT_H 0x09 -#define KXCJ9_ZOUT_L 0x0a -#define KXCJ9_ZOUT_H 0x0b -#define KXCJ9_DCST_RESP 0x0c -#define KXCJ9_WHOAMI 0x0f -#define KXCJ9_INT_SRC1 0x16 -#define KXCJ9_INT_SRC2 0x17 -#define KXCJ9_STATUS 0x18 -#define KXCJ9_INT_REL 0x1a -#define KXCJ9_CTRL1 0x1b -#define KXCJ9_CTRL2 0x1d -#define KXCJ9_INT_CTRL1 0x1e -#define KXCJ9_INT_CTRL2 0x1f -#define KXCJ9_DATA_CTRL 0x21 -#define KXCJ9_WAKEUP_TIMER 0x29 -#define KXCJ9_SELF_TEST 0x3a -#define KXCJ9_WAKEUP_THRESHOLD 0x6a - -#define KXCJ9_INT_SRC1_WUFS BIT(1) -#define KXCJ9_INT_SRC1_DRDY BIT(4) - -#define KXCJ9_INT_SRC2_ZPWU BIT(0) -#define KXCJ9_INT_SRC2_ZNWU BIT(1) -#define KXCJ9_INT_SRC2_YPWU BIT(2) -#define KXCJ9_INT_SRC2_YNWU BIT(3) -#define KXCJ9_INT_SRC2_XPWU BIT(4) -#define KXCJ9_INT_SRC2_XNWU BIT(5) - -#define KXCJ9_STATUS_INT BIT(4) - -#define KXCJ9_CTRL1_WUFE BIT(1) -#define KXCJ9_CTRL1_DRDYE BIT(5) -#define KXCJ9_CTRL1_PC1 BIT(7) - -#define KXCJ9_GSEL_2G (0 << 3) -#define KXCJ9_GSEL_4G BIT(3) -#define KXCJ9_GSEL_8G (2 << 3) -#define KXCJ9_GSEL_8G_14BIT (3 << 3) -#define KXCJ9_GSEL_ALL (3 << 3) - -#define KXCJ9_RES_8BIT (0 << 6) -#define KXCJ9_RES_12BIT BIT(6) - -#define KXCJ9_CTRL2_OWUF (7 << 0) -#define KXCJ9_CTRL2_DCST BIT(4) -#define KXCJ9_CTRL2_SRST BIT(7) - -#define KXCJ9_OWUF_0_781HZ 0 -#define KXCJ9_OWUF_1_563HZ 1 -#define KXCJ9_OWUF_3_125HZ 2 -#define KXCJ9_OWUF_6_250HZ 3 -#define KXCJ9_OWUF_12_50HZ 4 -#define KXCJ9_OWUF_25_00HZ 5 -#define KXCJ9_OWUF_50_00HZ 6 -#define KXCJ9_OWUF_100_0HZ 7 - -#define KXCJ9_INT_CTRL1_IEL BIT(3) -#define KXCJ9_INT_CTRL1_IEA BIT(4) -#define KXCJ9_INT_CTRL1_IEN BIT(5) - -#define KXCJ9_INT_CTRL2_ZPWUE BIT(0) -#define KXCJ9_INT_CTRL2_ZNWUE BIT(1) -#define KXCJ9_INT_CTRL2_YPWUE BIT(2) -#define KXCJ9_INT_CTRL2_YNWUE BIT(3) -#define KXCJ9_INT_CTRL2_XPWUE BIT(4) -#define KXCJ9_INT_CTRL2_XNWUE BIT(5) - -#define KXCJ9_OSA_0_000HZ 0 -#define KXCJ9_OSA_0_781HZ 8 -#define KXCJ9_OSA_1_563HZ 9 -#define KXCJ9_OSA_3_125HZ 0xa -#define KXCJ9_OSA_6_250HZ 0xb -#define KXCJ9_OSA_12_50HZ 0 -#define KXCJ9_OSA_25_00HZ 1 -#define KXCJ9_OSA_50_00HZ 2 -#define KXCJ9_OSA_100_0HZ 3 -#define KXCJ9_OSA_200_0HZ 4 -#define KXCJ9_OSA_400_0HZ 5 -#define KXCJ9_OSA_800_0HZ 6 -#define KXCJ9_OSA_1600_HZ 7 -#define KXCJ9_OSA_FIELD 0xf - -/* Min and Max sampling frequency in mHz */ -#define KXCJ9_ACCEL_MIN_FREQ 12500 -#define KXCJ9_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) - -#endif /* __CROS_EC_ACCEL_KXCJ9_H */ |