diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-01-31 13:43:04 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-11 19:53:06 -0700 |
| commit | 554ba87174803e1ae52165ad46b9b22500b1ebb8 (patch) | |
| tree | da013d28d7da998255c11cbc120ca549c548a69b /driver/accel_lis2dh.h | |
| parent | 31fb76dc641dfdcdbde2fd6447168967d6c5c1c2 (diff) | |
| download | chrome-ec-554ba87174803e1ae52165ad46b9b22500b1ebb8.tar.gz | |
driver: lis2dh: Add support for lng2dm
Looking at 4.19 kernel (drivers/iio/accel/st_accel_core.c),
LNG2DM has the same interface as LIS2DH but a resolution of 8 bits only.
In consequence, basic handling of LIS2DE and LNG2DM should be identical.
FIFO and interrupt are not supported.
BUG=b:122281217
BRANCH=none
TEST=TBD
Change-Id: I7b715cfccdaf147dcdc002e9be8f5231a3dd8f98
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1449112
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'driver/accel_lis2dh.h')
| -rw-r--r-- | driver/accel_lis2dh.h | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/driver/accel_lis2dh.h b/driver/accel_lis2dh.h index 824127b90c..691cca6865 100644 --- a/driver/accel_lis2dh.h +++ b/driver/accel_lis2dh.h @@ -3,21 +3,30 @@ * found in the LICENSE file. */ -/* LIS2DH accelerometer module for Chrome EC */ +/* LIS2DH/LIS2DE/LNG2DM accelerometer module for Chrome EC */ #ifndef __CROS_EC_ACCEL_LIS2DH_H #define __CROS_EC_ACCEL_LIS2DH_H #include "driver/stm_mems_common.h" -#define LIS2DH_I2C_ADDR(__x) (__x << 1) +/* + * LIS2DH/LIS2DE: + * + * 8-bit address is 0011 00XW b. Where 'X' is determined + * by the voltage on the ADDR pin, and 'W' is read write bit + */ +#define LIS2DH_ADDR0 0x30 +#define LIS2DH_ADDR1 0x32 /* - * 7-bit address is 000110Xb. Where 'X' is determined - * by the voltage on the ADDR pin + * LNG2DM: + * + * 8-bit address is 0101 00XW b. Where 'X' is determined + * by the voltage on the ADDR pin, and 'W' is read write bit */ -#define LIS2DH_ADDR0 LIS2DH_I2C_ADDR(0x18) -#define LIS2DH_ADDR1 LIS2DH_I2C_ADDR(0x19) +#define LNG2DM_ADDR0 0x50 +#define LNG2DM_ADDR1 0x52 /* Who Am I */ #define LIS2DH_WHO_AM_I_REG 0x0f @@ -107,11 +116,13 @@ enum lis2dh_odr { /* * Sensor resolution in number of bits + * * lis2dh has variable precision (8/10/12 bits) depending Power Mode * selected, here Only Normal Power mode supported (10 bits). - * But for lis2de, it has only one 8bit resolution. + * + * lis2de/lng2dm only support 8bit resolution. */ -#ifdef CONFIG_ACCEL_LIS2DE +#if defined(CONFIG_ACCEL_LIS2DE) || defined(CONFIG_ACCEL_LNG2DM) #define LIS2DH_RESOLUTION 8 #elif defined(CONFIG_ACCEL_LIS2DH) #define LIS2DH_RESOLUTION 10 |