Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 166 insertions, 172 deletions

diff --git a/driver/accelgyro_icm42607.h b/driver/accelgyro_icm42607.h
index e2d2b3469a..53ae7a37df 100644
--- a/driver/accelgyro_icm42607.h
+++ b/driver/accelgyro_icm42607.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,59 +15,55 @@
  * 7-bit address is 110100Xb. Where 'X' is determined
  * by the logic level on pin AP_AD0.
  */
-#define ICM42607_ADDR0_FLAGS		0x68
-#define ICM42607_ADDR1_FLAGS		0x69
+#define ICM42607_ADDR0_FLAGS 0x68
+#define ICM42607_ADDR1_FLAGS 0x69
 
 /* Min and Max sampling frequency in mHz */
-#define ICM42607_ACCEL_MIN_FREQ		1562
-#define ICM42607_ACCEL_MAX_FREQ		\
-		MOTION_MAX_SENSOR_FREQUENCY(400000, 100000)
-#define ICM42607_GYRO_MIN_FREQ		12500
-#define ICM42607_GYRO_MAX_FREQ		\
-		MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
+#define ICM42607_ACCEL_MIN_FREQ 1562
+#define ICM42607_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(400000, 100000)
+#define ICM42607_GYRO_MIN_FREQ 12500
+#define ICM42607_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
 
 /* Min and Max Accel FS in g */
-#define ICM42607_ACCEL_FS_MIN_VAL	2
-#define ICM42607_ACCEL_FS_MAX_VAL	16
+#define ICM42607_ACCEL_FS_MIN_VAL 2
+#define ICM42607_ACCEL_FS_MAX_VAL 16
 
 /* Min and Max Gyro FS in dps */
-#define ICM42607_GYRO_FS_MIN_VAL	250
-#define ICM42607_GYRO_FS_MAX_VAL	2000
+#define ICM42607_GYRO_FS_MIN_VAL 250
+#define ICM42607_GYRO_FS_MAX_VAL 2000
 
 /* accel stabilization time in us */
-#define ICM42607_ACCEL_START_TIME	20000
-#define ICM42607_ACCEL_STOP_TIME	0
+#define ICM42607_ACCEL_START_TIME 20000
+#define ICM42607_ACCEL_STOP_TIME 0
 
 /* gyro stabilization time in us */
-#define ICM42607_GYRO_START_TIME	40000
-#define ICM42607_GYRO_STOP_TIME		20000
+#define ICM42607_GYRO_START_TIME 40000
+#define ICM42607_GYRO_STOP_TIME 20000
 
 /* Reg value from Accel FS in G */
-#define ICM42607_ACCEL_FS_TO_REG(_fs)	((_fs) <= 2 ? 3 : \
-					 (_fs) >= 16 ? 0 : \
-					 3 - __fls((_fs) / 2))
+#define ICM42607_ACCEL_FS_TO_REG(_fs) \
+	((_fs) <= 2 ? 3 : (_fs) >= 16 ? 0 : 3 - __fls((_fs) / 2))
 
 /* Accel FSR in G from Reg value */
-#define ICM42607_ACCEL_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 2)
+#define ICM42607_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2)
 
 /* Reg value from Gyro FS in dps */
-#define ICM42607_GYRO_FS_TO_REG(_fs)	((_fs) <= 250 ? 3 : \
-					 (_fs) >= 2000 ? 0 : \
-					 3 - __fls((_fs) / 250))
+#define ICM42607_GYRO_FS_TO_REG(_fs) \
+	((_fs) <= 250 ? 3 : (_fs) >= 2000 ? 0 : 3 - __fls((_fs) / 250))
 
 /* Gyro FSR in dps from Reg value */
-#define ICM42607_GYRO_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 250)
+#define ICM42607_GYRO_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 250)
 
 /* Reg value from ODR in mHz */
-#define ICM42607_ODR_TO_REG(_odr)	((_odr) == 0 ? 0 : \
-					 (__fls(1600000 / (_odr)) + 5))
+#define ICM42607_ODR_TO_REG(_odr) \
+	((_odr) == 0 ? 0 : (__fls(1600000 / (_odr)) + 5))
 
 /* ODR in mHz from Reg value */
-#define ICM42607_REG_TO_ODR(_reg)	((_reg) <= 5 ? 1600000 : \
-					 (1600000 / (1 << ((_reg) - 5))))
+#define ICM42607_REG_TO_ODR(_reg) \
+	((_reg) <= 5 ? 1600000 : (1600000 / (1 << ((_reg)-5))))
 
 /* Reg value for the next higher ODR */
-#define ICM42607_ODR_REG_UP(_reg)	((_reg) - 1)
+#define ICM42607_ODR_REG_UP(_reg) ((_reg)-1)
 
 /*
  * Filter bandwidth values from ODR reg
@@ -77,10 +73,8 @@
  *   50Hz (10) -> 25Hz (6)
  *   <= 25Hz (11) -> 16Hz (7)
  */
-#define ICM42607_ODR_TO_FILT_BW(_odr)	((_odr) <= 7 ? 1 : \
-					 (_odr) <= 9 ? (_odr) - 5 : \
-					 (_odr) == 10 ? 6 : \
-					 7)
+#define ICM42607_ODR_TO_FILT_BW(_odr) \
+	((_odr) <= 7 ? 1 : (_odr) <= 9 ? (_odr)-5 : (_odr) == 10 ? 6 : 7)
 
 /*
  * Register addresses are virtual address on 16 bits.
@@ -88,53 +82,53 @@
  * and LSB real register address.
  * ex: MREG2 (block 0x28) register 03 => 0x2803
  */
-#define ICM42607_REG_MCLK_RDY		0x0000
-#define ICM42607_MCLK_RDY		BIT(3)
+#define ICM42607_REG_MCLK_RDY 0x0000
+#define ICM42607_MCLK_RDY BIT(3)
 
-#define ICM42607_REG_DEVICE_CONFIG	0x0001
-#define ICM42607_SPI_MODE_1_2		BIT(0)
-#define ICM42607_SPI_AP_4WIRE		BIT(2)
+#define ICM42607_REG_DEVICE_CONFIG 0x0001
+#define ICM42607_SPI_MODE_1_2 BIT(0)
+#define ICM42607_SPI_AP_4WIRE BIT(2)
 
-#define ICM42607_REG_SIGNAL_PATH_RESET	0x0002
-#define ICM42607_SOFT_RESET_DEV_CONFIG	BIT(4)
-#define ICM42607_FIFO_FLUSH		BIT(2)
+#define ICM42607_REG_SIGNAL_PATH_RESET 0x0002
+#define ICM42607_SOFT_RESET_DEV_CONFIG BIT(4)
+#define ICM42607_FIFO_FLUSH BIT(2)
 
-#define ICM42607_REG_DRIVE_CONFIG1	0x0003
+#define ICM42607_REG_DRIVE_CONFIG1 0x0003
 
-#define ICM42607_REG_DRIVE_CONFIG2	0x0004
+#define ICM42607_REG_DRIVE_CONFIG2 0x0004
 
-#define ICM42607_REG_DRIVE_CONFIG3	0x0005
+#define ICM42607_REG_DRIVE_CONFIG3 0x0005
 
 /* default int configuration is pulsed mode, open drain, and active low */
-#define ICM42607_REG_INT_CONFIG		0x0006
-#define ICM42607_INT2_MASK		GENMASK(5, 3)
-#define ICM42607_INT2_LATCHED		BIT(5)
-#define ICM42607_INT2_PUSH_PULL		BIT(4)
-#define ICM42607_INT2_ACTIVE_HIGH	BIT(3)
-#define ICM42607_INT1_MASK		GENMASK(2, 0)
-#define ICM42607_INT1_LATCHED		BIT(2)
-#define ICM42607_INT1_PUSH_PULL		BIT(1)
-#define ICM42607_INT1_ACTIVE_HIGH	BIT(0)
+#define ICM42607_REG_INT_CONFIG 0x0006
+#define ICM42607_INT2_MASK GENMASK(5, 3)
+#define ICM42607_INT2_LATCHED BIT(5)
+#define ICM42607_INT2_PUSH_PULL BIT(4)
+#define ICM42607_INT2_ACTIVE_HIGH BIT(3)
+#define ICM42607_INT1_MASK GENMASK(2, 0)
+#define ICM42607_INT1_LATCHED BIT(2)
+#define ICM42607_INT1_PUSH_PULL BIT(1)
+#define ICM42607_INT1_ACTIVE_HIGH BIT(0)
 
 /* data are 16 bits */
-#define ICM42607_REG_TEMP_DATA		0x0009
+#define ICM42607_REG_TEMP_DATA 0x0009
 
 /* X + Y + Z: 3 * 16 bits */
-#define ICM42607_REG_ACCEL_DATA_XYZ	0x000B
-#define ICM42607_REG_GYRO_DATA_XYZ	0x0011
+#define ICM42607_REG_ACCEL_DATA_XYZ 0x000B
+#define ICM42607_REG_GYRO_DATA_XYZ 0x0011
 
-#define ICM42607_INVALID_DATA		-32768
+#define ICM42607_INVALID_DATA -32768
 
 /* data are 16 bits */
-#define ICM42607_REG_TMST_FSYNCH	0x0017
+#define ICM42607_REG_TMST_FSYNCH 0x0017
 
-#define ICM42607_REG_PWR_MGMT0		0x001F
-#define ICM42607_ACCEL_LP_CLK_SEL	BIT(7)
-#define ICM42607_IDLE			BIT(4)
-#define ICM42607_GYRO_MODE_MASK		GENMASK(3, 2)
-#define ICM42607_GYRO_MODE(_m)		(((_m) & 0x03) << 2)
-#define ICM42607_ACCEL_MODE_MASK	GENMASK(1, 0)
-#define ICM42607_ACCEL_MODE(_m)		((_m) & 0x03)
+#define ICM42607_REG_PWR_MGMT0 0x001F
+#define ICM42607_ACCEL_LP_CLK_SEL BIT(7)
+#define ICM42607_IDLE BIT(4)
+#define ICM42607_GYRO_MODE_MASK GENMASK(3, 2)
+#define ICM42607_GYRO_MODE(_m) (((_m)&0x03) << 2)
+#define ICM42607_ACCEL_MODE_MASK GENMASK(1, 0)
+#define ICM42607_ACCEL_MODE(_m) ((_m)&0x03)
 
 enum icm42607_sensor_mode {
 	ICM42607_MODE_OFF,
@@ -143,14 +137,14 @@ enum icm42607_sensor_mode {
 	ICM42607_MODE_LOW_NOISE,
 };
 
-#define ICM42607_REG_GYRO_CONFIG0	0x0020
-#define ICM42607_REG_ACCEL_CONFIG0	0x0021
-#define ICM42607_FS_MASK		GENMASK(6, 5)
-#define ICM42607_FS_SEL(_fs)		(((_fs) & 0x03) << 5)
-#define ICM42607_ODR_MASK		GENMASK(3, 0)
-#define ICM42607_ODR(_odr)		((_odr) & 0x0F)
+#define ICM42607_REG_GYRO_CONFIG0 0x0020
+#define ICM42607_REG_ACCEL_CONFIG0 0x0021
+#define ICM42607_FS_MASK GENMASK(6, 5)
+#define ICM42607_FS_SEL(_fs) (((_fs)&0x03) << 5)
+#define ICM42607_ODR_MASK GENMASK(3, 0)
+#define ICM42607_ODR(_odr) ((_odr)&0x0F)
 
-#define ICM42607_REG_TEMP_CONFIG0	0x0022
+#define ICM42607_REG_TEMP_CONFIG0 0x0022
 
 enum icm42607_ui_avg {
 	ICM42607_UI_AVG_2X,
@@ -172,122 +166,122 @@ enum icm42607_ui_filt_bw {
 	ICM42607_UI_FILT_BW_16HZ,
 };
 
-#define ICM42607_REG_GYRO_CONFIG1	0x0023
-#define ICM42607_REG_ACCEL_CONFIG1	0x0024
-#define ICM42607_UI_AVG_MASK		GENMASK(6, 4)
-#define ICM42607_UI_AVG_SET(_avg)	(((_avg) & 0x07) << 4)
-#define ICM42607_UI_FILT_BW_MASK	GENMASK(2, 0)
-#define ICM42607_UI_FILT_BW_SET(_filt)	((_filt) & 0x07)
+#define ICM42607_REG_GYRO_CONFIG1 0x0023
+#define ICM42607_REG_ACCEL_CONFIG1 0x0024
+#define ICM42607_UI_AVG_MASK GENMASK(6, 4)
+#define ICM42607_UI_AVG_SET(_avg) (((_avg)&0x07) << 4)
+#define ICM42607_UI_FILT_BW_MASK GENMASK(2, 0)
+#define ICM42607_UI_FILT_BW_SET(_filt) ((_filt)&0x07)
 
-#define ICM42607_REG_FIFO_CONFIG1	0x0028
-#define ICM42607_REG_FIFO_CONFIG2	0x0029
-#define ICM42607_REG_FIFO_CONFIG3	0x002A
-#define ICM42607_FIFO_STOP_ON_FULL_MODE	BIT(1)
-#define ICM42607_FIFO_BYPASS		BIT(0)
-#define ICM42607_FIFO_MODE_STREAM	0x00
+#define ICM42607_REG_FIFO_CONFIG1 0x0028
+#define ICM42607_REG_FIFO_CONFIG2 0x0029
+#define ICM42607_REG_FIFO_CONFIG3 0x002A
+#define ICM42607_FIFO_STOP_ON_FULL_MODE BIT(1)
+#define ICM42607_FIFO_BYPASS BIT(0)
+#define ICM42607_FIFO_MODE_STREAM 0x00
 
 /* FIFO watermark value is 16 bits little endian */
-#define ICM42607_REG_FIFO_WM		0x0029
-
-#define ICM42607_REG_INT_SOURCE0	0x002B
-#define ICM42607_ST_INT1_EN		BIT(7)
-#define ICM42607_FSYNC_INT1_EN		BIT(6)
-#define ICM42607_PLL_RDY_INT1_EN	BIT(5)
-#define ICM42607_RESET_DONE_INT1_EN	BIT(4)
-#define ICM42607_DRDY_INT1_EN		BIT(3)
-#define ICM42607_FIFO_THS_INT1_EN	BIT(2)
-#define ICM42607_FIFO_FULL_INT1_EN	BIT(1)
-#define ICM42607_UI_AGC_RDY_INT1_EN	BIT(0)
-
-#define ICM42607_REG_INTF_CONFIG0	0x0035
-#define ICM42607_FIFO_COUNT_FORMAT	BIT(6)
-#define ICM42607_FIFO_COUNT_ENDIAN	BIT(5)
-#define ICM42607_SENSOR_DATA_ENDIAN	BIT(4)
-
-#define ICM42607_REG_INTF_CONFIG1	0x0036
-#define ICM42607_I3C_SDR_EN		BIT(3)
-#define ICM42607_I3C_DDR_EN		BIT(2)
-#define ICM42607_CLKSEL_MASK		GENMASK(1, 0)
-#define ICM42607_CLKSEL_PLL_ENABLE	0x01
-
-#define ICM42607_REG_INT_STATUS_DRDY	0x0039
-#define ICM42607_DATA_RDY_INT		BIT(0)
-
-#define ICM42607_REG_INT_STATUS		0x003A
-#define ICM42607_ST_INT			BIT(7)
-#define ICM42607_FSYNC_INT		BIT(6)
-#define ICM42607_PLL_RDY_INT		BIT(5)
-#define ICM42607_RESET_DONE_INT		BIT(4)
-#define ICM42607_FIFO_THS_INT		BIT(2)
-#define ICM42607_FIFO_FULL_INT		BIT(1)
-#define ICM42607_AGC_RDY_INT		BIT(0)
+#define ICM42607_REG_FIFO_WM 0x0029
+
+#define ICM42607_REG_INT_SOURCE0 0x002B
+#define ICM42607_ST_INT1_EN BIT(7)
+#define ICM42607_FSYNC_INT1_EN BIT(6)
+#define ICM42607_PLL_RDY_INT1_EN BIT(5)
+#define ICM42607_RESET_DONE_INT1_EN BIT(4)
+#define ICM42607_DRDY_INT1_EN BIT(3)
+#define ICM42607_FIFO_THS_INT1_EN BIT(2)
+#define ICM42607_FIFO_FULL_INT1_EN BIT(1)
+#define ICM42607_UI_AGC_RDY_INT1_EN BIT(0)
+
+#define ICM42607_REG_INTF_CONFIG0 0x0035
+#define ICM42607_FIFO_COUNT_FORMAT BIT(6)
+#define ICM42607_FIFO_COUNT_ENDIAN BIT(5)
+#define ICM42607_SENSOR_DATA_ENDIAN BIT(4)
+
+#define ICM42607_REG_INTF_CONFIG1 0x0036
+#define ICM42607_I3C_SDR_EN BIT(3)
+#define ICM42607_I3C_DDR_EN BIT(2)
+#define ICM42607_CLKSEL_MASK GENMASK(1, 0)
+#define ICM42607_CLKSEL_PLL_ENABLE 0x01
+
+#define ICM42607_REG_INT_STATUS_DRDY 0x0039
+#define ICM42607_DATA_RDY_INT BIT(0)
+
+#define ICM42607_REG_INT_STATUS 0x003A
+#define ICM42607_ST_INT BIT(7)
+#define ICM42607_FSYNC_INT BIT(6)
+#define ICM42607_PLL_RDY_INT BIT(5)
+#define ICM42607_RESET_DONE_INT BIT(4)
+#define ICM42607_FIFO_THS_INT BIT(2)
+#define ICM42607_FIFO_FULL_INT BIT(1)
+#define ICM42607_AGC_RDY_INT BIT(0)
 
 /* FIFO count is 16 bits */
-#define ICM42607_REG_FIFO_COUNT		0x003D
+#define ICM42607_REG_FIFO_COUNT 0x003D
 
-#define ICM42607_REG_FIFO_DATA		0x003F
+#define ICM42607_REG_FIFO_DATA 0x003F
 
-#define ICM42607_REG_APEX_CONFIG0	0x0025
-#define ICM42607_DMP_SRAM_RESET_APEX	BIT(0)
+#define ICM42607_REG_APEX_CONFIG0 0x0025
+#define ICM42607_DMP_SRAM_RESET_APEX BIT(0)
 
-#define ICM42607_REG_APEX_CONFIG1	0x0026
-#define ICM42607_DMP_ODR_50HZ		BIT(1)
+#define ICM42607_REG_APEX_CONFIG1 0x0026
+#define ICM42607_DMP_ODR_50HZ BIT(1)
 
-#define ICM42607_REG_WHO_AM_I		0x0075
-#define ICM42607_CHIP_ICM42607P		0x60
+#define ICM42607_REG_WHO_AM_I 0x0075
+#define ICM42607_CHIP_ICM42607P 0x60
 
 /* MREG read access registers */
-#define ICM42607_REG_BLK_SEL_W		0x0079
-#define ICM42607_REG_MADDR_W		0x007A
-#define ICM42607_REG_M_W		0x007B
+#define ICM42607_REG_BLK_SEL_W 0x0079
+#define ICM42607_REG_MADDR_W 0x007A
+#define ICM42607_REG_M_W 0x007B
 
 /* MREG write access registers */
-#define ICM42607_REG_BLK_SEL_R		0x007C
-#define ICM42607_REG_MADDR_R		0x007D
-#define ICM42607_REG_M_R		0x007E
+#define ICM42607_REG_BLK_SEL_R 0x007C
+#define ICM42607_REG_MADDR_R 0x007D
+#define ICM42607_REG_M_R 0x007E
 
 /* USER BANK MREG1 */
-#define ICM42607_MREG_FIFO_CONFIG5	0x0001
-#define ICM42607_FIFO_WM_GT_TH		BIT(5)
-#define ICM42607_FIFO_RESUME_PARTIAL_RD	BIT(4)
-#define ICM42607_FIFO_HIRES_EN		BIT(3)
-#define ICM42607_FIFO_TMST_FSYNC_EN	BIT(2)
-#define ICM42607_FIFO_GYRO_EN		BIT(1)
-#define ICM42607_FIFO_ACCEL_EN		BIT(0)
-
-#define ICM42607_MREG_OTP_CONFIG	0x002B
-#define ICM42607_OTP_COPY_MODE_MASK	GENMASK(3, 2)
-#define ICM42607_OTP_COPY_TRIM		(0x01 << 2)
-#define ICM42607_OTP_COPY_ST_DATA	(0x03 << 2)
-
-#define ICM42607_MREG_INT_SOURCE7	0x0030
-#define ICM42607_MREG_INT_SOURCE8	0x0031
-#define ICM42607_MREG_INT_SOURCE9	0x0032
-#define ICM42607_MREG_INT_SOURCE10	0x0033
-
-#define ICM42607_MREG_APEX_CONFIG2	0x0044
-#define ICM42607_MREG_APEX_CONFIG3	0x0045
-#define ICM42607_MREG_APEX_CONFIG4	0x0046
-#define ICM42607_MREG_APEX_CONFIG5	0x0047
-#define ICM42607_MREG_APEX_CONFIG9	0x0048
-#define ICM42607_MREG_APEX_CONFIG10	0x0049
-#define ICM42607_MREG_APEX_CONFIG11	0x004A
-#define ICM42607_MREG_APEX_CONFIG12	0x0067
-
-#define ICM42607_MREG_OFFSET_USER0	0x004E
-#define ICM42607_MREG_OFFSET_USER1	0x004F
-#define ICM42607_MREG_OFFSET_USER2	0x0050
-#define ICM42607_MREG_OFFSET_USER3	0x0051
-#define ICM42607_MREG_OFFSET_USER4	0x0052
-#define ICM42607_MREG_OFFSET_USER5	0x0053
-#define ICM42607_MREG_OFFSET_USER6	0x0054
-#define ICM42607_MREG_OFFSET_USER7	0x0055
-#define ICM42607_MREG_OFFSET_USER8	0x0056
+#define ICM42607_MREG_FIFO_CONFIG5 0x0001
+#define ICM42607_FIFO_WM_GT_TH BIT(5)
+#define ICM42607_FIFO_RESUME_PARTIAL_RD BIT(4)
+#define ICM42607_FIFO_HIRES_EN BIT(3)
+#define ICM42607_FIFO_TMST_FSYNC_EN BIT(2)
+#define ICM42607_FIFO_GYRO_EN BIT(1)
+#define ICM42607_FIFO_ACCEL_EN BIT(0)
+
+#define ICM42607_MREG_OTP_CONFIG 0x002B
+#define ICM42607_OTP_COPY_MODE_MASK GENMASK(3, 2)
+#define ICM42607_OTP_COPY_TRIM (0x01 << 2)
+#define ICM42607_OTP_COPY_ST_DATA (0x03 << 2)
+
+#define ICM42607_MREG_INT_SOURCE7 0x0030
+#define ICM42607_MREG_INT_SOURCE8 0x0031
+#define ICM42607_MREG_INT_SOURCE9 0x0032
+#define ICM42607_MREG_INT_SOURCE10 0x0033
+
+#define ICM42607_MREG_APEX_CONFIG2 0x0044
+#define ICM42607_MREG_APEX_CONFIG3 0x0045
+#define ICM42607_MREG_APEX_CONFIG4 0x0046
+#define ICM42607_MREG_APEX_CONFIG5 0x0047
+#define ICM42607_MREG_APEX_CONFIG9 0x0048
+#define ICM42607_MREG_APEX_CONFIG10 0x0049
+#define ICM42607_MREG_APEX_CONFIG11 0x004A
+#define ICM42607_MREG_APEX_CONFIG12 0x0067
+
+#define ICM42607_MREG_OFFSET_USER0 0x004E
+#define ICM42607_MREG_OFFSET_USER1 0x004F
+#define ICM42607_MREG_OFFSET_USER2 0x0050
+#define ICM42607_MREG_OFFSET_USER3 0x0051
+#define ICM42607_MREG_OFFSET_USER4 0x0052
+#define ICM42607_MREG_OFFSET_USER5 0x0053
+#define ICM42607_MREG_OFFSET_USER6 0x0054
+#define ICM42607_MREG_OFFSET_USER7 0x0055
+#define ICM42607_MREG_OFFSET_USER8 0x0056
 
 /* USER BANK MREG2 */
-#define ICM42607_MREG_OTP_CTRL7		0x2806
-#define ICM42607_OTP_RELOAD		BIT(3)
-#define ICM42607_OTP_PWR_DOWN		BIT(1)
+#define ICM42607_MREG_OTP_CTRL7 0x2806
+#define ICM42607_OTP_RELOAD BIT(3)
+#define ICM42607_OTP_PWR_DOWN BIT(1)
 
 extern const struct accelgyro_drv icm42607_drv;