driver: lsm6dsm: Clean register definition

Remove duplicates and order registers by address.

BUG=b:115587004
BRANCH=none
TEST=Buildall

Change-Id: I31a1c5f18314a67c6ec0de64fa69bd5723c60a05
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/1361988
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Justin TerAvest <teravest@chromium.org>
Tested-by: Justin TerAvest <teravest@chromium.org>
Trybot-Ready: Justin TerAvest <teravest@chromium.org>

1 files changed, 83 insertions, 53 deletions

diff --git a/driver/accelgyro_lsm6dsm.h b/driver/accelgyro_lsm6dsm.h
index 0d0480a9cb..8575bfe158 100644
--- a/driver/accelgyro_lsm6dsm.h
+++ b/driver/accelgyro_lsm6dsm.h
@@ -19,22 +19,53 @@
 #define LSM6DSM_ADDR0			LSM6DSM_I2C_ADDR(0x6a)
 #define LSM6DSM_ADDR1			LSM6DSM_I2C_ADDR(0x6b)
 
+/* COMMON DEFINE FOR ACCEL-GYRO SENSORS */
+#define LSM6DSM_EN_BIT			0x01
+#define LSM6DSM_DIS_BIT			0x00
+
 /* Access to embedded sensor hub register bank */
 #define LSM6DSM_FUNC_CFG_ACC_ADDR	0x01
 #define LSM6DSM_FUNC_CFG_EN			0x80
 #define LSM6DSM_FUNC_CFG_EN_B			0x20
 
-/* Who Am I */
-#define LSM6DSM_WHO_AM_I_REG		0x0f
-#define LSM6DSM_WHO_AM_I		0x6a
+/* FIFO decimator registers and bitmask */
+#define LSM6DSM_FIFO_CTRL1_ADDR		0x06
 
-/* COMMON DEFINE FOR ACCEL-GYRO SENSORS */
-#define LSM6DSM_EN_BIT			0x01
-#define LSM6DSM_DIS_BIT			0x00
+/* Output data rate registers and masks */
+#define LSM6DSM_ODR_REG(_sensor) \
+	(LSM6DSM_CTRL1_ADDR + _sensor)
+#define LSM6DSM_ODR_MASK		0xf0
 
+#define LSM6DSM_FIFO_CTRL2_ADDR		0x07
 
-#define LSM6DSM_GYRO_OUT_X_L_ADDR	0x22
-#define LSM6DSM_ACCEL_OUT_X_L_ADDR	0x28
+#define LSM6DSM_FIFO_CTRL3_ADDR		0x08
+#define LSM6DSM_FIFO_DEC_XL_OFF			0
+#define LSM6DSM_FIFO_DEC_G_OFF			3
+
+#define LSM6DSM_FIFO_CTRL4_ADDR		0x09
+
+#define LSM6DSM_FIFO_DECIMATOR(_dec) \
+	(_dec < 8 ? _dec : (2 + __builtin_ctz(_dec)))
+
+/* Hardware FIFO size in byte */
+#define LSM6DSM_MAX_FIFO_SIZE		4096
+#define LSM6DSM_MAX_FIFO_LENGTH	(LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
+
+#define LSM6DSM_FIFO_CTRL5_ADDR		0x0a
+#define LSM6DSM_FIFO_CTRL5_ODR_OFF		3
+#define LSM6DSM_FIFO_CTRL5_ODR_MASK \
+	(0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF)
+#define LSM6DSM_FIFO_CTRL5_MODE_MASK		0x07
+
+#define LSM6DSM_INT1_CTRL		0x0d
+#define LSM6DSM_INT_FIFO_TH			0x08
+#define LSM6DSM_INT_FIFO_OVR			0x10
+#define LSM6DSM_INT_FIFO_FULL			0x20
+#define LSM6DSM_INT_SIGMO			0x40
+
+/* Who Am I */
+#define LSM6DSM_WHO_AM_I_REG		0x0f
+#define LSM6DSM_WHO_AM_I			0x6a
 
 #define LSM6DSM_CTRL1_ADDR		0x10
 #define LSM6DSM_XL_ODR_MASK			0xf0
@@ -55,42 +86,29 @@
 #define LSM6DSM_CTRL7_ADDR		0x16
 
 #define LSM6DSM_CTRL10_ADDR		0x19
-#define LSM6DSM_EMBED_FUNC_EN			0x4
+#define LSM6DSM_FUNC_EN_MASK			0x04
+#define LSM6DSM_SIG_MOT_MASK			0x01
+#define LSM6DSM_EMBED_FUNC_EN			0x04
+#define LSM6DSM_SIG_MOT_EN			0x01
 
+/* Master mode configuration register */
 #define LSM6DSM_MASTER_CFG_ADDR		0x1a
-#define LSM6DSM_I2C_MASTER_ON			0x1
-#define LSM6DSM_I2C_PASS_THRU_MODE		0x4
+#define LSM6DSM_PASSTROUGH_MASK			0x1f
 #define LSM6DSM_EXT_TRIGGER_EN			0x10
+#define LSM6DSM_PULLUP_EN			0x08
+#define LSM6DSM_I2C_PASS_THRU_MODE		0x04
+#define LSM6DSM_I2C_MASTER_ON			0x01
 
-#define LSM6DSM_STATUS_REG		0x1e
-
-/* Output data rate registers and masks */
-#define LSM6DSM_ODR_REG(_sensor) \
-	(LSM6DSM_CTRL1_ADDR + _sensor)
-#define LSM6DSM_ODR_MASK		0xf0
-
-/* Hardware FIFO size in byte */
-#define LSM6DSM_MAX_FIFO_SIZE		4096
-#define LSM6DSM_MAX_FIFO_LENGTH	(LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
-
-/* FIFO decimator registers and bitmask */
-#define LSM6DSM_FIFO_CTRL1_ADDR		0x06
-#define LSM6DSM_FIFO_CTRL2_ADDR		0x07
+#define LSM6DSM_TAP_SRC_ADDR		0x1c
+#define LSM6DSM_STAP_DETECT			0x20
+#define LSM6DSM_DTAP_DETECT			0x10
 
-#define LSM6DSM_FIFO_CTRL3_ADDR		0x08
-#define LSM6DSM_FIFO_DEC_XL_OFF			0
-#define LSM6DSM_FIFO_DEC_G_OFF			3
-
-#define LSM6DSM_FIFO_CTRL4_ADDR		0x09
+#define LSM6DSM_STATUS_REG		0x1e
 
-#define LSM6DSM_FIFO_DECIMATOR(_dec) \
-	(_dec < 8 ? _dec : (2 + __builtin_ctz(_dec)))
+#define LSM6DSM_GYRO_OUT_X_L_ADDR	0x22
+#define LSM6DSM_ACCEL_OUT_X_L_ADDR	0x28
 
-#define LSM6DSM_INT1_CTRL		0x0d
-#define LSM6DSM_INT_FIFO_TH			0x08
-#define LSM6DSM_INT_FIFO_OVR			0x10
-#define LSM6DSM_INT_FIFO_FULL			0x20
-#define LSM6DSM_INT_SIGMO			0x40
+#define LSM6DSM_SENSORHUB1_REG		0x2e
 
 #define LSM6DSM_FIFO_STS1_ADDR		0x3a
 #define LSM6DSM_FIFO_STS2_ADDR		0x3b
@@ -99,27 +117,43 @@
 #define LSM6DSM_FIFO_FULL			0x2000
 #define LSM6DSM_FIFO_DATA_OVR			0x4000
 #define LSM6DSM_FIFO_WATERMARK			0x8000
-#define LSM6DSM_FIFO_NODECIM		0x01
+#define LSM6DSM_FIFO_NODECIM			0x01
 
 /* Out data register */
 #define LSM6DSM_FIFO_DATA_ADDR		0x3e
 
 /* Registers value for supported FIFO mode */
-#define LSM6DSM_FIFO_MODE_BYPASS_VAL	0x00
+#define LSM6DSM_FIFO_MODE_BYPASS_VAL		0x00
 #define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL	0x06
 
-#define LSM6DSM_FIFO_CTRL5_ADDR		0x0a
-#define LSM6DSM_FIFO_CTRL5_ODR_OFF		3
-#define LSM6DSM_FIFO_CTRL5_ODR_MASK \
-	(0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF)
-#define LSM6DSM_FIFO_CTRL5_MODE_MASK		0x07
+#define LSM6DSM_FUNC_SRC1_ADDR		0x53
+#define LSM6DSM_SENSORHUB_END_OP		0x01
+#define LSM6DSM_SIGN_MOTION_IA			0x40
 
-/* Define ODR FIFO values. Max value is max ODR for sensors
- * Value is limited to 416 Hz
- */
+#define LSM6DSM_LIR_ADDR		0x58
+#define LSM6DSM_LIR_MASK			0x01
+#define LSM6DSM_EN_INT				0x80
+#define LSM6DSM_EN_TAP				0x0e
+#define LSM6DSM_TAP_MASK			0x8e
 
+#define LSM6DSM_TAP_THS_6D		0x59
+#define LSM6DSM_D4D_EN_MASK			0x80
+#define LSM6DSM_TAP_TH_MASK			0x1f
 
-/* Register values for Sensor Hub Slave 0 */
+#define LSM6DSM_INT_DUR2_ADDR		0x5a
+#define LSM6DSM_TAP_DUR_MASK			0xf0
+#define LSM6DSM_TAP_QUIET_MASK			0x0c
+
+#define LSM6DSM_WUP_THS_ADDR		0x5b
+#define LSM6DSM_S_D_TAP_MASK			0x80
+#define LSM6DSM_STAP_EN				0
+#define LSM6DSM_DTAP_EN				1
+
+#define LSM6DSM_MD1_CFG_ADDR		0x5e
+#define LSM6DSM_INT1_STAP			0x40
+#define LSM6DSM_INT1_DTAP			0x08
+
+/* Register values for Sensor Hub Slave 0 / Bank A */
 #define LSM6DSM_SLV0_ADD_ADDR		0x02
 #define LSM6DSM_SLV0_ADDR_SHFT			1
 #define LSM6DSM_SLV0_ADDR_MASK			0xfe
@@ -137,11 +171,7 @@
 #define LSM6DSM_SLV1_CONFIG_ADDR	0x07
 #define LSM6DSM_SLV0_WR_ONCE_MASK		0x20
 
-#define LSM6DSM_SENSORHUB1_REG		0x2e
-
-/* Registers value for sensor Hub */
-#define LSM6DSM_FUNC_SRC1		0x53
-#define LSM6DSM_SENSORHUB_END_OP	0x01
+#define LSM6DSM_DATA_WRITE_SUB_SLV0_ADDR 0x0e
 
 /* Define device available in FIFO pattern */
 enum dev_fifo {