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| author | Scott Collyer <scollyer@google.com> | 2020-01-10 13:18:27 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-14 22:04:26 +0000 |
| commit | 98bd02f3e2e7fbe6224d8656d1d3555aa2f88de5 (patch) | |
| tree | a1290ef7971a901275962b371bafe54f9cc064ce /driver/charger/bq25710.c | |
| parent | e39204e43ca3b075654285ddb94a028774b51666 (diff) | |
| download | chrome-ec-98bd02f3e2e7fbe6224d8656d1d3555aa2f88de5.tar.gz | |
bq25710: Ensure low power mode is disabled when reading reg 0x3E
The bq25710 relies on voltage divider connected to the CELL_BATPRESZ
pin in order to set the correct value for VSYS_MIN for different
battery types (1S - 4S). The voltage divider is connected to VDDA.
This circuit is not powered when the bq25710 is in low power mode,
which is the default mode when AC is not connected. This CL ensures
that bq25710 is not in low power mode, prior to reading the value of
MinSystemVoltage (register 0x3E).
BUG=b:142087417
BRANCH=firmware-hatch-12672.B
TEST=On Kohaku, without AC power removed battery connection, then
reconnected the battery and verfied that register 0x3E had the
expected value for a 2S battery.
Change-Id: Ib008813cab15a4b4c7ee2ec7e411282e54b37d0b
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1993911
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Commit-Queue: Shelley Chen <shchen@chromium.org>
Diffstat (limited to 'driver/charger/bq25710.c')
| -rw-r--r-- | driver/charger/bq25710.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/driver/charger/bq25710.c b/driver/charger/bq25710.c index 8e418ea103..c4035d2f1b 100644 --- a/driver/charger/bq25710.c +++ b/driver/charger/bq25710.c @@ -21,6 +21,14 @@ #error "BQ25710 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC." #endif +/* + * Delay required from taking the bq25710 out of low power mode and having the + * correct value in register 0x3E for VSYS_MIN voltage. The length of the delay + * was determined by experiment. Less than 12 msec was not enough of delay, so + * the value here is set to 20 msec to have plenty of margin. + */ +#define BQ25710_VDDA_STARTUP_DELAY_MSEC 20 + /* Sense resistor configurations and macros */ #define DEFAULT_SENSE_RESISTOR 10 @@ -184,9 +192,14 @@ static void bq25710_init(void) * this chip so without a full power cycle, some registers may not be at * their default values. Note, need to save the POR value of * MIN_SYSTEM_VOLTAGE register prior to setting the reset so that the - * correct value is preserved. + * correct value is preserved. In order to have the correct value read, + * the bq25710 must not be in low power mode, otherwise the VDDA rail + * may not be powered if AC is not connected. */ - rv = raw_read16(BQ25710_REG_MIN_SYSTEM_VOLTAGE, &vsys); + rv = bq25710_set_low_power_mode(0); + /* Allow enough time for VDDA to be powered */ + msleep(BQ25710_VDDA_STARTUP_DELAY_MSEC); + rv |= raw_read16(BQ25710_REG_MIN_SYSTEM_VOLTAGE, &vsys); rv |= raw_read16(BQ25710_REG_CHARGE_OPTION_3, ®); if (!rv) { reg |= BQ25710_CHARGE_OPTION_3_RESET_REG; @@ -195,6 +208,8 @@ static void bq25710_init(void) /* Restore VSYS_MIN voltage to POR reset value */ raw_write16(BQ25710_REG_MIN_SYSTEM_VOLTAGE, vsys); } + /* Reenable low power mode */ + bq25710_set_low_power_mode(1); if (!raw_read16(BQ25710_REG_PROCHOT_OPTION_1, ®)) { /* Disbale VDPM prochot profile at initialization */ |