common: bit change 1 << constants with BIT(constants)

Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.

Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]

BUG=None
BRANCH=None
TEST=None

Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

2 files changed, 40 insertions, 40 deletions

diff --git a/driver/charger/bd9995x.c b/driver/charger/bd9995x.c
index 9ab69a7c38..1eba3e9aa6 100644
--- a/driver/charger/bd9995x.c
+++ b/driver/charger/bd9995x.c
@@ -1507,7 +1507,7 @@ static int bd9995x_psys_charger_adc(void)
 	 * Calculate power in mW
 	 * PSYS = VACP×IACP+VBAT×IBAT = IPMON / GPMON
 	 */
-	return (int) ((ipmon * 1000) / ((1 << BD9995X_PSYS_GAIN_SELECT) *
+	return (int) ((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) *
 		BD9995X_PMON_IOUT_ADC_READ_COUNT));
 }
 
diff --git a/driver/charger/rt946x.h b/driver/charger/rt946x.h
index b28a87f3f5..0f7bcb2426 100644
--- a/driver/charger/rt946x.h
+++ b/driver/charger/rt946x.h
@@ -246,14 +246,14 @@
 #define RT946X_SHIFT_DB_RST	1
 #define RT946X_SHIFT_REG_RST	0
 
-#define RT946X_MASK_RST		(1 << RT946X_SHIFT_RST)
-#define RT946X_MASK_CHG_RST	(1 << RT946X_SHIFT_CHG_RST)
-#define RT946X_MASK_FLED_RST	(1 << RT946X_SHIFT_FLED_RST)
-#define RT946X_MASK_LDO_RST	(1 << RT946X_SHIFT_LDO_RST)
-#define RT946X_MASK_RGB_RST	(1 << RT946X_SHIFT_RGB_RST)
-#define RT946X_MASK_BL_RST	(1 << RT946X_SHIFT_BL_RST)
-#define RT946X_MASK_DB_RST	(1 << RT946X_SHIFT_DB_RST)
-#define RT946X_MASK_REG_RST	(1 << RT946X_SHIFT_REG_RST)
+#define RT946X_MASK_RST		BIT(RT946X_SHIFT_RST)
+#define RT946X_MASK_CHG_RST	BIT(RT946X_SHIFT_CHG_RST)
+#define RT946X_MASK_FLED_RST	BIT(RT946X_SHIFT_FLED_RST)
+#define RT946X_MASK_LDO_RST	BIT(RT946X_SHIFT_LDO_RST)
+#define RT946X_MASK_RGB_RST	BIT(RT946X_SHIFT_RGB_RST)
+#define RT946X_MASK_BL_RST	BIT(RT946X_SHIFT_BL_RST)
+#define RT946X_MASK_DB_RST	BIT(RT946X_SHIFT_DB_RST)
+#define RT946X_MASK_REG_RST	BIT(RT946X_SHIFT_REG_RST)
 #define RT946X_MASK_SOFT_RST                                                   \
 	(RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST |    \
 	 RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST |       \
@@ -263,8 +263,8 @@
 #define RT946X_SHIFT_OPA_MODE   0
 #define RT946X_SHIFT_HZ_EN      2
 
-#define RT946X_MASK_OPA_MODE	(1 << RT946X_SHIFT_OPA_MODE)
-#define RT946X_MASK_HZ_EN	(1 << RT946X_SHIFT_HZ_EN)
+#define RT946X_MASK_OPA_MODE	BIT(RT946X_SHIFT_OPA_MODE)
+#define RT946X_MASK_HZ_EN	BIT(RT946X_SHIFT_HZ_EN)
 
 /* ========== CHGCTRL2 0x02 ============ */
 #define RT946X_SHIFT_SHIP_MODE	7
@@ -273,11 +273,11 @@
 #define RT946X_SHIFT_CFO_EN	1
 #define RT946X_SHIFT_CHG_EN	0
 
-#define RT946X_MASK_SHIP_MODE	(1 << RT946X_SHIFT_SHIP_MODE)
-#define RT946X_MASK_TE		(1 << RT946X_SHIFT_TE)
+#define RT946X_MASK_SHIP_MODE	BIT(RT946X_SHIFT_SHIP_MODE)
+#define RT946X_MASK_TE		BIT(RT946X_SHIFT_TE)
 #define RT946X_MASK_ILMTSEL	(0x3 << RT946X_SHIFT_ILMTSEL)
-#define RT946X_MASK_CFO_EN	(1 << RT946X_SHIFT_CFO_EN)
-#define RT946X_MASK_CHG_EN	(1 << RT946X_SHIFT_CHG_EN)
+#define RT946X_MASK_CFO_EN	BIT(RT946X_SHIFT_CFO_EN)
+#define RT946X_MASK_CHG_EN	BIT(RT946X_SHIFT_CHG_EN)
 
 /* ========== RSTPASCODE1 0x03 (mt6370) ============ */
 #define MT6370_MASK_RSTPASCODE1	0xA9
@@ -287,7 +287,7 @@
 #define RT946X_SHIFT_ILIMEN	0
 
 #define RT946X_MASK_AICR	(0x3F << RT946X_SHIFT_AICR)
-#define RT946X_MASK_ILIMEN	(1 << RT946X_SHIFT_ILIMEN)
+#define RT946X_MASK_ILIMEN	BIT(RT946X_SHIFT_ILIMEN)
 
 /* ========== RSTPASCODE2 0x04 (mt6370) ============ */
 #define MT6370_MASK_RSTPASCODE2	0x96
@@ -332,31 +332,31 @@
 /* ========== CHGCTRL12 0x0C ============ */
 #define RT946X_SHIFT_TMR_EN	1
 
-#define RT946X_MASK_TMR_EN	(1 << RT946X_SHIFT_TMR_EN)
+#define RT946X_MASK_TMR_EN	BIT(RT946X_SHIFT_TMR_EN)
 
 /* ========== CHGCTRL13 0x0D ============ */
 #define RT946X_SHIFT_WDT_EN	7
 
-#define RT946X_MASK_WDT_EN	(1 << RT946X_SHIFT_WDT_EN)
+#define RT946X_MASK_WDT_EN	BIT(RT946X_SHIFT_WDT_EN)
 
 /* ========== CHGCTRL14 0x0E ============ */
 #define RT946X_SHIFT_AICLMEAS	7
 #define RT946X_SHIFT_AICLVTH	0
 
-#define RT946X_MASK_AICLMEAS	(1 << RT946X_SHIFT_AICLMEAS)
+#define RT946X_MASK_AICLMEAS	BIT(RT946X_SHIFT_AICLMEAS)
 #define RT946X_MASK_AICLVTH	0x07
 
 /* ========== CHGCTRL16 0x10 ============ */
 #define RT946X_SHIFT_JEITA_EN	4
 
-#define RT946X_MASK_JEITA_EN	(1 << RT946X_SHIFT_JEITA_EN)
+#define RT946X_MASK_JEITA_EN	BIT(RT946X_SHIFT_JEITA_EN)
 
 /* ========== CHGADC 0x11 ============ */
 #define RT946X_SHIFT_ADC_IN_SEL	4
 #define RT946X_SHIFT_ADC_START	0
 
 #define RT946X_MASK_ADC_IN_SEL	(0xF << RT946X_SHIFT_ADC_IN_SEL)
-#define RT946X_MASK_ADC_START	(1 << RT946X_SHIFT_ADC_START)
+#define RT946X_MASK_ADC_START	BIT(RT946X_SHIFT_ADC_START)
 
 /* ========== CHGDPDM1 0x12 (rt946x) DEVICETYPE 0x22 (mt6370) ============ */
 #define RT946X_SHIFT_USBCHGEN	7
@@ -364,10 +364,10 @@
 #define RT946X_SHIFT_CDP	1
 #define RT946X_SHIFT_SDP	0
 
-#define RT946X_MASK_USBCHGEN	(1 << RT946X_SHIFT_USBCHGEN)
-#define RT946X_MASK_DCP		(1 << RT946X_SHIFT_DCP)
-#define RT946X_MASK_CDP		(1 << RT946X_SHIFT_CDP)
-#define RT946X_MASK_SDP		(1 << RT946X_SHIFT_SDP)
+#define RT946X_MASK_USBCHGEN	BIT(RT946X_SHIFT_USBCHGEN)
+#define RT946X_MASK_DCP		BIT(RT946X_SHIFT_DCP)
+#define RT946X_MASK_CDP		BIT(RT946X_SHIFT_CDP)
+#define RT946X_MASK_SDP		BIT(RT946X_SHIFT_SDP)
 
 #define RT946X_MASK_BC12_TYPE	(RT946X_MASK_DCP | \
 				 RT946X_MASK_CDP | \
@@ -401,7 +401,7 @@
 #define RT946X_SHIFT_ADC_STAT	0
 
 #define RT946X_MASK_CHG_STAT	(0x3 << RT946X_SHIFT_CHG_STAT)
-#define RT946X_MASK_ADC_STAT	(1 << RT946X_SHIFT_ADC_STAT)
+#define RT946X_MASK_ADC_STAT	BIT(RT946X_SHIFT_ADC_STAT)
 
 /* ========== CHGNTC 0x43 ============ */
 #define RT946X_SHIFT_BATNTC_FAULT	4
@@ -411,7 +411,7 @@
 /* ========== CHGSTATC 0x50 (rt946x) ============ */
 #define RT946X_SHIFT_PWR_RDY    7
 
-#define RT946X_MASK_PWR_RDY     (1 << RT946X_SHIFT_PWR_RDY)
+#define RT946X_MASK_PWR_RDY     BIT(RT946X_SHIFT_PWR_RDY)
 
 /* ========== CHGFAULT 0x51 (rt946x) ============ */
 #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
@@ -420,10 +420,10 @@
 #define RT946X_SHIFT_CHG_VBATOV	6
 #define RT946X_SHIFT_CHG_VBUSOV	7
 
-#define RT946X_MASK_CHG_VSYSUV	(1 << RT946X_SHIFT_CHG_VSYSUV)
-#define RT946X_MASK_CHG_VSYSOV	(1 << RT946X_SHIFT_CHG_VSYSOV)
-#define RT946X_MASK_CHG_VBATOV	(1 << RT946X_SHIFT_CHG_VBATOV)
-#define RT946X_MASK_CHG_VBUSOV	(1 << RT946X_SHIFT_CHG_VBUSOV)
+#define RT946X_MASK_CHG_VSYSUV	BIT(RT946X_SHIFT_CHG_VSYSUV)
+#define RT946X_MASK_CHG_VSYSOV	BIT(RT946X_SHIFT_CHG_VSYSOV)
+#define RT946X_MASK_CHG_VBATOV	BIT(RT946X_SHIFT_CHG_VBATOV)
+#define RT946X_MASK_CHG_VBUSOV	BIT(RT946X_SHIFT_CHG_VBUSOV)
 #endif
 
 /* ========== DPDMIRQ 0x56 ============ */
@@ -431,21 +431,21 @@
 #define RT946X_SHIFT_DPDMIRQ_DETACH	1
 #define RT946X_SHIFT_DPDMIRQ_ATTACH	0
 
-#define RT946X_MASK_DPDMIRQ_DETACH	(1 << RT946X_SHIFT_DPDMIRQ_DETACH)
-#define RT946X_MASK_DPDMIRQ_ATTACH	(1 << RT946X_SHIFT_DPDMIRQ_ATTACH)
+#define RT946X_MASK_DPDMIRQ_DETACH	BIT(RT946X_SHIFT_DPDMIRQ_DETACH)
+#define RT946X_MASK_DPDMIRQ_ATTACH	BIT(RT946X_SHIFT_DPDMIRQ_ATTACH)
 #endif
 
 
 /* ========== LDOCFG 0x80 (mt6370) ============ */
 #define MT6370_SHIFT_LDOCFG_OMS	6
 
-#define MT6370_MASK_LDOCFG_OMS		(1 << MT6370_SHIFT_LDOCFG_OMS)
+#define MT6370_MASK_LDOCFG_OMS		BIT(MT6370_SHIFT_LDOCFG_OMS)
 
 /* ========== LDOVOUT 0x81 (mt6370) ============ */
 #define MT6370_SHIFT_LDOVOUT_EN		7
 #define MT6370_SHIFT_LDOVOUT_VOUT	0
 
-#define MT6370_MASK_LDOVOUT_EN		(1 << MT6370_SHIFT_LDOVOUT_EN)
+#define MT6370_MASK_LDOVOUT_EN		BIT(MT6370_SHIFT_LDOVOUT_EN)
 #define MT6370_MASK_LDOVOUT_VOUT	(0xf << MT6370_SHIFT_LDOVOUT_VOUT)
 
 /* ========== RGBDIM 0x82/0x83/0x84 (mt6370) ============ */
@@ -464,9 +464,9 @@
 #define MT6370_SHIFT_RGB_ISNK3DIM	5
 #define MT6370_SHIFT_RGB_ISNKDIM_BASE	8
 
-#define MT6370_MASK_RGB_ISNK1DIM_EN	(1 << MT6370_SHIFT_RGB_ISNK1DIM)
-#define MT6370_MASK_RGB_ISNK2DIM_EN	(1 << MT6370_SHIFT_RGB_ISNK2DIM)
-#define MT6370_MASK_RGB_ISNK3DIM_EN	(1 << MT6370_SHIFT_RGB_ISNK3DIM)
+#define MT6370_MASK_RGB_ISNK1DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK1DIM)
+#define MT6370_MASK_RGB_ISNK2DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK2DIM)
+#define MT6370_MASK_RGB_ISNK3DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK3DIM)
 #define MT6370_MASK_RGB_ISNK_ALL_EN	(MT6370_MASK_RGB_ISNK1DIM_EN | \
 					 MT6370_MASK_RGB_ISNK2DIM_EN | \
 					 MT6370_MASK_RGB_ISNK3DIM_EN)
@@ -500,8 +500,8 @@
 
 #define RT946X_MASK_CHG_VBATOV		MT6370_SHIFT_CHG_VBATOV_STAT
 
-#define MT6370_MASK_CHG_VBUSOV_STAT	(1 << MT6370_SHIFT_CHG_VBUSOV_STAT)
-#define MT6370_MASK_CHG_VBATOV_STAT	(1 << MT6370_SHIFT_CHG_VBATOV_STAT)
+#define MT6370_MASK_CHG_VBUSOV_STAT	BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)
+#define MT6370_MASK_CHG_VBATOV_STAT	BIT(MT6370_SHIFT_CHG_VBATOV_STAT)
 #endif
 
 /* ========== Variant-specific configuration ============ */