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| author | Denis Brockus <dbrockus@chromium.org> | 2019-06-25 12:44:16 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-07-19 21:11:02 +0000 |
| commit | d1a18f82ed831d4e640336ff5571f5fa64bc7b36 (patch) | |
| tree | c46aeb6136de1c27c66e3d5f662e9620161bef7b /driver/ppc/nx20p348x.h | |
| parent | 1f14229fa7e499dfcee07d17add187598ff0a46c (diff) | |
| download | chrome-ec-d1a18f82ed831d4e640336ff5571f5fa64bc7b36.tar.gz | |
Use 7bit I2C/SPI slave addresses in EC
Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'driver/ppc/nx20p348x.h')
| -rw-r--r-- | driver/ppc/nx20p348x.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index 531842d766..a04868c732 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -8,15 +8,15 @@ #ifndef __CROS_EC_NX20P348X_H #define __CROS_EC_NX20P348X_H -#define NX20P3483_ADDR0 0xE0 -#define NX20P3483_ADDR1 0xE2 -#define NX20P3483_ADDR2 0xE4 -#define NX20P3483_ADDR3 0xE6 - -#define NX20P3481_ADDR0 0xE8 -#define NX20P3481_ADDR1 0xEA -#define NX20P3481_ADDR2 0xEC -#define NX20P3481_ADDR3 0xEE +#define NX20P3483_ADDR0__7bf (0x70) +#define NX20P3483_ADDR1__7bf (0x71) +#define NX20P3483_ADDR2__7bf (0x72) +#define NX20P3483_ADDR3__7bf (0x73) + +#define NX20P3481_ADDR0__7bf (0x74) +#define NX20P3481_ADDR1__7bf (0x75) +#define NX20P3481_ADDR2__7bf (0x76) +#define NX20P3481_ADDR3__7bf (0x77) /* * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery |