diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
| commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
| tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /driver/ppc/nx20p348x.h | |
| parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
| download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz | |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'driver/ppc/nx20p348x.h')
| -rw-r--r-- | driver/ppc/nx20p348x.h | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index 68048be6ea..531842d766 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -40,10 +40,10 @@ #define NX20P348X_DEVICE_CONTROL_REG 0x0B /* Device Control Register */ -#define NX20P348X_CTRL_FRS_AT (1 << 3) -#define NX20P348X_CTRL_DB_EXIT (1 << 2) -#define NX20P348X_CTRL_VBUSDIS_EN (1 << 1) -#define NX20P348X_CTRL_LDO_SD (1 << 0) +#define NX20P348X_CTRL_FRS_AT BIT(3) +#define NX20P348X_CTRL_DB_EXIT BIT(2) +#define NX20P348X_CTRL_VBUSDIS_EN BIT(1) +#define NX20P348X_CTRL_LDO_SD BIT(0) /* Device Status Modes */ #define NX20P348X_DEVICE_MODE_MASK 0x7 @@ -59,14 +59,14 @@ #define NX20P3483_MODE_STANDBY 4 /* Switch Control Register */ -#define NX20P348X_SWITCH_CONTROL_HVSNK (1 << 0) -#define NX20P348X_SWITCH_CONTROL_HVSRC (1 << 1) -#define NX20P348X_SWITCH_CONTROL_5VSRC (1 << 2) +#define NX20P348X_SWITCH_CONTROL_HVSNK BIT(0) +#define NX20P348X_SWITCH_CONTROL_HVSRC BIT(1) +#define NX20P348X_SWITCH_CONTROL_5VSRC BIT(2) /* Switch Status Register */ -#define NX20P348X_HVSNK_STS (1 << 0) -#define NX20P348X_HVSRC_STS (1 << 1) -#define NX20P348X_5VSRC_STS (1 << 2) +#define NX20P348X_HVSNK_STS BIT(0) +#define NX20P348X_HVSRC_STS BIT(1) +#define NX20P348X_5VSRC_STS BIT(2) #define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25 #define NX20P348X_SWITCH_STATUS_MASK 0x7 @@ -100,23 +100,23 @@ #define NX20P348X_OVLO_23_0 6 /* Interrupt 1 Register Bits */ -#define NX20P348X_INT1_DBEXIT_ERR (1 << 7) -#define NX20P348X_INT1_FRS_DET (1 << 6) -#define NX20P348X_INT1_OV_5VSRC (1 << 4) -#define NX20P348X_INT1_RCP_5VSRC (1 << 3) -#define NX20P348X_INT1_SC_5VSRC (1 << 2) -#define NX20P348X_INT1_OC_5VSRC (1 << 1) -#define NX20P348X_INT1_OTP (1 << 0) +#define NX20P348X_INT1_DBEXIT_ERR BIT(7) +#define NX20P348X_INT1_FRS_DET BIT(6) +#define NX20P348X_INT1_OV_5VSRC BIT(4) +#define NX20P348X_INT1_RCP_5VSRC BIT(3) +#define NX20P348X_INT1_SC_5VSRC BIT(2) +#define NX20P348X_INT1_OC_5VSRC BIT(1) +#define NX20P348X_INT1_OTP BIT(0) /* Interrupt 2 Register Bits */ -#define NX20P348X_INT2_EN_ERR (1 << 7) -#define NX20P348X_INT2_RCP_HVSNK (1 << 6) -#define NX20P348X_INT2_SC_HVSNK (1 << 5) -#define NX20P348X_INT2_OV_HVSNK (1 << 4) -#define NX20P348X_INT2_RCP_HVSRC (1 << 3) -#define NX20P348X_INT2_SC_HVSRC (1 << 2) -#define NX20P348X_INT2_OC_HVSRC (1 << 1) -#define NX20P348X_INT2_OV_HVSRC (1 << 0) +#define NX20P348X_INT2_EN_ERR BIT(7) +#define NX20P348X_INT2_RCP_HVSNK BIT(6) +#define NX20P348X_INT2_SC_HVSNK BIT(5) +#define NX20P348X_INT2_OV_HVSNK BIT(4) +#define NX20P348X_INT2_RCP_HVSRC BIT(3) +#define NX20P348X_INT2_SC_HVSRC BIT(2) +#define NX20P348X_INT2_OC_HVSRC BIT(1) +#define NX20P348X_INT2_OV_HVSRC BIT(0) struct ppc_drv; extern const struct ppc_drv nx20p348x_drv; |