diff options
author | Ting Shen <phoenixshen@google.com> | 2021-11-05 16:01:10 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2022-02-10 10:45:14 +0000 |
commit | 8a88dd4833708c0401b1cc1951f846fa574d4086 (patch) | |
tree | 4ff003bad0cc398a24ccdca71f9808150862e1eb /driver/ppc/rt1739.h | |
parent | f05dfc5d84616ec31c2fa96b06f6ecf6313f2698 (diff) | |
download | chrome-ec-8a88dd4833708c0401b1cc1951f846fa574d4086.tar.gz |
driver: implement rt1739 ppc/bc12 driver
Implement basic ppc/bc1.2 functions for Richtek rt1739 ppc.
BUG=b:200107774
TEST=manually verified source/sink/vconn functions
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Id500979262cea9fab7b38dfaff9339762896d0ef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3263230
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'driver/ppc/rt1739.h')
-rw-r--r-- | driver/ppc/rt1739.h | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/driver/ppc/rt1739.h b/driver/ppc/rt1739.h new file mode 100644 index 0000000000..43cc04f366 --- /dev/null +++ b/driver/ppc/rt1739.h @@ -0,0 +1,116 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Richtek RT1739 Type-C Power Path Controller */ + +#ifndef __CROS_EC_PPC_RT1739_H +#define __CROS_EC_PPC_RT1739_H + +#include "usb_charge.h" +#include "usbc_ppc.h" + +#define RT1739_ADDR1 0x70 +#define RT1739_ADDR2 0x71 +#define RT1739_ADDR3 0x72 +#define RT1739_ADDR4 0x73 + +#define RT1739_REG_DEVICE_ID0 0x02 +#define RT1739_DEVICE_ID_ES1 0x11 +#define RT1739_DEVICE_ID_ES2 0x12 + +#define RT1739_REG_SW_RESET 0x04 +#define RT1739_SW_RESET BIT(0) + +#define RT1739_REG_INT_MASK5 0x0D +#define RT1739_BC12_SNK_DONE_MASK BIT(0) + +#define RT1739_REG_INT_EVENT5 0x15 +#define RT1739_BC12_SNK_DONE_INT BIT(0) + +#define RT1739_REG_INT_STS4 0x1C +#define RT1739_VBUS_VALID BIT(2) +#define RT1739_VBUS_PRESENT BIT(0) + +#define RT1739_REG_SYS_CTRL 0x20 +#define RT1739_OT_EN BIT(4) +#define RT1739_SHUTDOWN_OFF BIT(0) + +#define RT1739_REG_VBUS_SWITCH_CTRL 0x21 +#define RT1739_LV_SRC_EN BIT(2) +#define RT1739_HV_SRC_EN BIT(1) +#define RT1739_HV_SNK_EN BIT(0) + +#define RT1739_REG_VBUS_OV_SETTING 0x24 + +#define RT1739_VBUS_OVP_SEL_SHIFT 0 +#define RT1739_VIN_HV_OVP_SEL_SHIFT 4 +#define RT1739_OVP_SEL_6_0V 0 +#define RT1739_OVP_SEL_6_8V 1 +#define RT1739_OVP_SEL_10_0V 2 +#define RT1739_OVP_SEL_11_5V 3 +#define RT1739_OVP_SEL_14_0V 4 +#define RT1739_OVP_SEL_17_0V 5 +#define RT1739_OVP_SEL_23_0V 6 + +#define RT1739_REG_VBUS_OC_SETTING 0x25 + +#define RT1739_LV_SRC_OCP_SEL_SHIFT 4 +#define RT1739_LV_SRC_OCP_SEL_1_25A 0 +#define RT1739_LV_SRC_OCP_SEL_1_75A 1 +#define RT1739_LV_SRC_OCP_SEL_2_25A 2 +#define RT1739_LV_SRC_OCP_SEL_3_3A 3 + +#define RT1739_HV_SINK_OCP_SEL_SHIFT 0 +#define RT1739_HV_SINK_OCP_SEL_1_25A 0 +#define RT1739_HV_SINK_OCP_SEL_1_75A 1 +#define RT1739_HV_SINK_OCP_SEL_3_3A 2 + +#define RT1739_VBUS_DAULT_DIS 0x26 +#define RT1739_OVP_DISVBUS_EN BIT(6) +#define RT1739_UVLO_DISVBUS_EN BIT(5) +#define RT1739_SRCP_DISVBUS_EN BIT(4) +#define RT1739_RCP_DISVBUS_EN BIT(3) +#define RT1739_SCP_DISVBUS_EN BIT(2) +#define RT1739_OCPS_DISVBUS_EN BIT(1) +#define RT1739_OCP_DISVBUS_EN BIT(0) + +#define RT1739_REG_VBUS_DET_EN 0x27 +#define RT1739_VBUS_SAFE5V_EN BIT(2) +#define RT1739_VBUS_SAFE0V_EN BIT(1) +#define RT1739_VBUS_PRESENT_EN BIT(0) + +#define RT1739_REG_VCONN_CTRL1 0x31 +#define RT1739_VCONN_ORIENT BIT(1) +#define RT1739_VCONN_EN BIT(0) + +#define RT1739_VCONN_ORIENT_CC1 MASK_SET +#define RT1739_VCONN_ORIENT_CC2 MASK_CLR + +#define RT1739_REG_VCONN_CTRL3 0x33 +#define RT1739_VCONN_CLIMIT_EN BIT(0) + +#define RT1739_REG_SBU_CTRL_01 0x38 +#define RT1739_SBUSW_MUX_SEL BIT(4) +#define RT1739_DM_SWEN BIT(1) +#define RT1739_DP_SWEN BIT(0) + +#define RT1739_REG_BC12_SNK_FUNC 0x40 +#define RT1739_BC12_SNK_EN BIT(7) + +#define RT1739_REG_BC12_STAT 0x41 +#define RT1739_PORT_STAT_MASK 0x0F +#define RT1739_PORT_STAT_SDP 0x0D +#define RT1739_PORT_STAT_CDP 0x0E +#define RT1739_PORT_STAT_DCP 0x0F + +#define RT1739_REG_SYS_CTRL1 0x60 +#define RT1739_OSC640K_FORCE_EN BIT(3) + +extern const struct ppc_drv rt1739_ppc_drv; +extern const struct bc12_drv rt1739_bc12_drv; + +void rt1739_interrupt(int port); + +#endif /* defined(__CROS_EC_PPC_RT1739_H) */ |