diff options
author | Denis Brockus <dbrockus@chromium.org> | 2019-06-25 12:44:16 -0600 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-07-19 21:11:02 +0000 |
commit | d1a18f82ed831d4e640336ff5571f5fa64bc7b36 (patch) | |
tree | c46aeb6136de1c27c66e3d5f662e9620161bef7b /driver/ppc/sn5s330.h | |
parent | 1f14229fa7e499dfcee07d17add187598ff0a46c (diff) | |
download | chrome-ec-d1a18f82ed831d4e640336ff5571f5fa64bc7b36.tar.gz |
Use 7bit I2C/SPI slave addresses in EC
Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'driver/ppc/sn5s330.h')
-rw-r--r-- | driver/ppc/sn5s330.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h index 6c79aa46ed..95f8fb4ac7 100644 --- a/driver/ppc/sn5s330.h +++ b/driver/ppc/sn5s330.h @@ -12,7 +12,7 @@ struct sn5s330_config { uint8_t i2c_port; - uint8_t i2c_addr; + uint8_t i2c_addr__7bf; }; extern const struct sn5s330_config sn5s330_chips[]; @@ -25,10 +25,10 @@ enum sn5s330_pp_idx { SN5S330_PP_COUNT, }; -#define SN5S330_ADDR0 0x80 -#define SN5S330_ADDR1 0x82 -#define SN5S330_ADDR2 0x84 -#define SN5S330_ADDR3 0x86 +#define SN5S330_ADDR0__7bf (0x40) +#define SN5S330_ADDR1__7bf (0x41) +#define SN5S330_ADDR2__7bf (0x42) +#define SN5S330_ADDR3__7bf (0x43) #define SN5S330_FUNC_SET1 0x50 #define SN5S330_FUNC_SET2 0x51 |