diff options
author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:08:36 -0700 |
---|---|---|
committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:59:38 -0700 |
commit | c453fd704268ef72de871b0c5ac7a989de662334 (patch) | |
tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /driver/retimer/anx7483.c | |
parent | 6c1587ca70f558b4f96b3f0b18ad8b027d3ba99d (diff) | |
parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
download | chrome-ec-c453fd704268ef72de871b0c5ac7a989de662334.tar.gz |
Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release
Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release
Relevant changes:
git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "panic_data_dartmonkey_v2.0.2887": PASSED
Test "panic_data_nocturne_fp_v2.2.64": PASSED
Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7
Diffstat (limited to 'driver/retimer/anx7483.c')
-rw-r--r-- | driver/retimer/anx7483.c | 300 |
1 files changed, 151 insertions, 149 deletions
diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index 6804fd3de8..2194483e44 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,11 +19,11 @@ * Programming guide specifies it may be as much as 30ms after chip power on * before it's ready for i2c */ -#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 +#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 #define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000 -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Tuning defaults */ struct anx7483_tuning_set { @@ -32,163 +32,162 @@ struct anx7483_tuning_set { }; static struct anx7483_tuning_set anx7483_usb_enabled[] = { - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dp_enabled[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_noflip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_flip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; -static inline int anx7483_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx7483_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx7483_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } @@ -231,6 +230,10 @@ static int anx7483_set(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + /* This driver treats safe mode as none */ + if (mux_state == USB_PD_MUX_SAFE_MODE) + mux_state = USB_PD_MUX_NONE; + /* * Mux is not powered in Z1 */ @@ -287,8 +290,7 @@ static enum ec_error_list anx7483_apply_tuning(const struct usb_mux *me, return EC_SUCCESS; } -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state) +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; @@ -324,7 +326,7 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, if (pin == ANX7483_PIN_UTX1) reg = ANX7483_UTX1_PORT_CFG0_REG; - else if (pin == ANX7483_PIN_UTX2) + else if (pin == ANX7483_PIN_UTX2) reg = ANX7483_UTX2_PORT_CFG0_REG; else if (pin == ANX7483_PIN_URX1) reg = ANX7483_URX1_PORT_CFG0_REG; |