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| author | Shaoliang Wang <swang@analogixsemi.com> | 2016-09-02 18:53:44 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-09-24 13:53:28 -0700 |
| commit | e29005abe7497988e14e0ef87f602a5417d003e6 (patch) | |
| tree | 2fe0e91397b1621ce648f8fbe78cbe1021e41603 /driver/tcpm/anx74xx.h | |
| parent | b94747d501ad7e4347b50c3ea55e615422d96212 (diff) | |
| download | chrome-ec-e29005abe7497988e14e0ef87f602a5417d003e6.tar.gz | |
anx74xx: fix hard reset issue.
1.ANX3429 have CC Rx buffer, when the partner sent one message,ANX3429
received this message into Rx buffer and triggered an interrupt to
inform (TCPM), at this moment Reef sends a CC message before reading
CC Rx buffer. After Reef sends this CC message successfully, it receives
the message the partner sent. So (TCPM) sees an unexpected message was
received, that`s why sends out hard reset.
Root cause:
ANX3429 use a normal R/W register as a interrupt status register.
Between EC read interrupt status and clear interrupt status, if
ANX3429 change interrupt status, it causes interrupt status is
incorrect on EC side.
Solution:
ANX3429 FW use two normal R/W registers for interrupt status reg,
one is for FW interrupt status,other is for EC control register.
Note:
Since cc messages conflict between TCPM and the Partner,ANX3429
shall discard the TCPM message, (TCPM) sometimes send soft reset
depend on the discarded message type.
2. Sometimes TCPM (Reef) does not response GoodCRC for a received mesg.
Root Cause: Reef send message conflict with ANX3429 send auto GoodCRC.
Solution: This is fixed in the 1.5 ANX 3429 firmware.
BUG=chrome-os-partner:53936
BRANCH=none
TEST=On Reef tested with ANX3429 FW v1.5, did not see HARD RST on
ec log with Zinger.
Change-Id: I81da95433e7a0cc71e7ed121b925afccbcd84b06
Signed-off-by: Swang <swang@analogixsemi.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/381014
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'driver/tcpm/anx74xx.h')
| -rw-r--r-- | driver/tcpm/anx74xx.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h index 8fc81c0bc0..6e31dbdf7d 100644 --- a/driver/tcpm/anx74xx.h +++ b/driver/tcpm/anx74xx.h @@ -152,6 +152,10 @@ #define ANX74XX_REG_PWR_ROLE_BIT_POS (2) #define ANX74XX_REG_DATA_ROLE_BIT_POS (1) +#define ANX74XX_REG_RECVD_MSG_INT 0x98 +#define ANX74XX_REG_CC_STATUS 0x99 +#define ANX74XX_REG_CTRL_FW 0x2E +#define CLEAR_RX_BUFFER (1) #define ANX74XX_REG_POWER_DOWN_CTRL 0x0d #define ANX74XX_REG_STATUS_CC1_VRD_USB (1 << 7) #define ANX74XX_REG_STATUS_CC1_VRD_1P5 (1 << 6) @@ -160,6 +164,19 @@ #define ANX74XX_REG_STATUS_CC2_VRD_1P5 (1 << 3) #define ANX74XX_REG_STATUS_CC2_VRD_3P0 (1 << 2) +/* defined in the inter-bock Spec: 4.2.10 CC Detect Status */ + +#define BIT_VALUE_OF_SRC_CC1_RD 0x01 +#define BIT_VALUE_OF_SRC_CC1_RA 0x02 +#define BIT_VALUE_OF_SNK_CC1_DEFAULT 0x04 +#define BIT_VALUE_OF_SNK_CC1_1_P_5 0x08 +#define BIT_VALUE_OF_SNK_CC1_3_P_0 0x0C +#define BIT_VALUE_OF_SRC_CC2_RD 0x10 +#define BIT_VALUE_OF_SRC_CC2_RA 0x20 +#define BIT_VALUE_OF_SNK_CC2_DEFAULT 0x40 +#define BIT_VALUE_OF_SNK_CC2_1_P_5 0x80 +#define BIT_VALUE_OF_SNK_CC2_3_P_0 0xC0 + extern const struct tcpm_drv anx74xx_tcpm_drv; extern const struct usb_mux_driver anx74xx_tcpm_usb_mux_driver; void anx74xx_tcpc_set_vbus(int port, int enable); |