diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:54:32 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-28 15:25:55 +0000 |
| commit | 6768d08a6964b710cc8d05eba20ba1b3cacbc528 (patch) | |
| tree | 9cd65863a4e8c6877de19d3c6bfde4bed0363d5c /driver/tcpm/ccgxxf.h | |
| parent | 7f4ab49140aeeda5adf20dac2d80a626dccbd6b5 (diff) | |
| download | chrome-ec-6768d08a6964b710cc8d05eba20ba1b3cacbc528.tar.gz | |
driver/tcpm/ccgxxf.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I14b6ee1c63e6db64b38190911e7c432f90b084cb
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730089
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'driver/tcpm/ccgxxf.h')
| -rw-r--r-- | driver/tcpm/ccgxxf.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h index 246a231d04..c20a6b18a6 100644 --- a/driver/tcpm/ccgxxf.h +++ b/driver/tcpm/ccgxxf.h @@ -10,15 +10,15 @@ #ifndef __CROS_EC_DRIVER_TCPM_CCGXXF_H #define __CROS_EC_DRIVER_TCPM_CCGXXF_H -#define CCGXXF_I2C_ADDR1_FLAGS 0x0B -#define CCGXXF_I2C_ADDR2_FLAGS 0x1B +#define CCGXXF_I2C_ADDR1_FLAGS 0x0B +#define CCGXXF_I2C_ADDR2_FLAGS 0x1B /* SBU FET control register */ -#define CCGXXF_REG_SBU_MUX_CTL 0xBB +#define CCGXXF_REG_SBU_MUX_CTL 0xBB /* F/W info register */ -#define CCGXXF_REG_FW_VERSION 0x94 -#define CCGXXF_REG_FW_VERSION_BUILD 0x96 +#define CCGXXF_REG_FW_VERSION 0x94 +#define CCGXXF_REG_FW_VERSION_BUILD 0x96 extern const struct tcpm_drv ccgxxf_tcpm_drv; @@ -45,13 +45,13 @@ enum ccgxxf_io_pins { CCGXXF_IO_7 }; -#define CCGXXF_REG_GPIO_CONTROL(port) ((port) + 0x80) -#define CCGXXF_REG_GPIO_STATUS(port) ((port) + 0x84) +#define CCGXXF_REG_GPIO_CONTROL(port) ((port) + 0x80) +#define CCGXXF_REG_GPIO_STATUS(port) ((port) + 0x84) -#define CCGXXF_REG_GPIO_MODE 0x88 -#define CCGXXF_GPIO_PIN_MASK_SHIFT 8 -#define CCGXXF_GPIO_PIN_MODE_SHIFT 2 -#define CCGXXF_GPIO_1P8V_SEL BIT(7) +#define CCGXXF_REG_GPIO_MODE 0x88 +#define CCGXXF_GPIO_PIN_MASK_SHIFT 8 +#define CCGXXF_GPIO_PIN_MODE_SHIFT 2 +#define CCGXXF_GPIO_1P8V_SEL BIT(7) enum ccgxxf_gpio_mode { CCGXXF_GPIO_MODE_HIZ_ANALOG, |