diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2016-06-07 10:02:02 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-14 22:00:58 -0700 |
| commit | 43552fb3f596573e0c633ad20fb313c21ddb281f (patch) | |
| tree | 51e58abbf6a2b62f589b972b6c34e7fce1a6d564 /driver/tcpm/it83xx.c | |
| parent | 4bb0efcc28d5c13721867f0bca1bfd3db68268b4 (diff) | |
| download | chrome-ec-43552fb3f596573e0c633ad20fb313c21ddb281f.tar.gz | |
it83xx: Support different PLL frequencies setting (24/48/96 MHz)
Default setting is at 48MHz.
For PLL frequency at 24MHz:
1. USB module can't work, it requires 48MHz to work.
2. SSPI clock frequency is divide by two.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. uart, i2c, timer, and pd modules are function normally
at different PLL frequency settings.
2. use 'flashrom' utility to flash EC binary with different
PLL settings.
Change-Id: Iabce4726baff493a6136136af18732b58df45d7f
Reviewed-on: https://chromium-review.googlesource.com/347551
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'driver/tcpm/it83xx.c')
| -rw-r--r-- | driver/tcpm/it83xx.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c index 3bc0c0db32..ed871edd02 100644 --- a/driver/tcpm/it83xx.c +++ b/driver/tcpm/it83xx.c @@ -262,8 +262,6 @@ static void it83xx_set_data_role(enum usbpd_port port, int pd_role) static void it83xx_init(enum usbpd_port port, int role) { - /* defalut PD Clock = PLL 48 / 6 = 8M. */ - IT83XX_ECPM_SCDCR4 = (IT83XX_ECPM_SCDCR4 & 0xf0) | 5; /* reset */ IT83XX_USBPD_GCR(port) = 0; USBPD_SW_RESET(port); |