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| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-12-04 18:05:14 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-11 22:16:49 +0000 |
| commit | d421419f1a2c095857d846d6107fe575a3b3571c (patch) | |
| tree | 83963e37cb7c70defbc37d6fc3d9a9588e6ad117 /driver/tcpm/it83xx_pd.h | |
| parent | e92c7a2a33a5dbc48c9ab8294c2c67a949dc1572 (diff) | |
| download | chrome-ec-d421419f1a2c095857d846d6107fe575a3b3571c.tar.gz | |
tcpm/it83xx: don't enable/disable Tx when Rx_enable() called
Register BMC PHY (00h bit4) enable/disable both Tx and Rx module,
and we shouldn't enable/disable Tx module when Rx_enable() called,
So I change to set Rx decode enable/disable only in Rx_enable().
Setting PD sleep mask shouldn't tie with Rx_enable(), so I change
to set sleep mask by HOOK_CONNECT/DISCONNECT. Enable deep sleep mode,
when all ITE ports are in Unattach.SRC/SNK state and other ports
aren't pd_capable(). Disable deep sleep mode, when one of ITE port is
in Attach.SRC/SNK state or one of other ports is pd_capable().
BUG=b:174151372
BRANCH=none
TEST=on drawcia, plug-in dongle and adapter:
1.console cmd "pd 0 hard", hard reset tx done is set within 1ms.
2.check PD sleep mask: nothing attached = 0, one port attached = 1
3.lid close to G3(Rd_5.1k), then plug-in adapter, can go to
SNK_READY state
4.can send SOP' to E-mark cable
5.console cmd "sysjump rw", can go to SNK/SRC_READY
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: Ibbf2f2d3d086be0bad4f3430c78f5ac3a26f8b1a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2573667
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'driver/tcpm/it83xx_pd.h')
| -rw-r--r-- | driver/tcpm/it83xx_pd.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h index 2b1f076a2d..401a74887d 100644 --- a/driver/tcpm/it83xx_pd.h +++ b/driver/tcpm/it83xx_pd.h @@ -51,7 +51,7 @@ #define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) #define USBPD_REG_MASK_MSG_RX_DONE BIT(4) #define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3) -#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(2) +#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE BIT(2) #define USBPD_REG_MASK_MSG_TX_DONE BIT(1) #define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0) #define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15) @@ -71,6 +71,7 @@ #define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5) #define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1A) #define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1B) +#define USBPD_REG_MASK_HARD_RESET_DECODE BIT(0) #define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1C) #define USBPD_REG_GET_SOP_TYPE_RX(mrsr) (((mrsr) >> 4) & 0x7) #define USBPD_REG_MASK_RX_MSG_VALID BIT(0) @@ -350,6 +351,9 @@ /* macros for PD ISR */ #define USBPD_IS_HARD_RESET_DETECT(port) \ IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_HARD_RESET_DETECT) +#define USBPD_IS_HARD_CABLE_RESET_TX_DONE(port) \ + IS_MASK_SET(IT83XX_USBPD_ISR(port), \ + USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE) #define USBPD_IS_TX_DONE(port) \ IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_TX_DONE) #define USBPD_IS_RX_DONE(port) \ |