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| author | Caveh Jalali <caveh@chromium.org> | 2019-07-30 17:45:59 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-08-14 10:23:31 +0000 |
| commit | ce1a0c9bdfa0b35455b9619fdb1b5794caa63894 (patch) | |
| tree | fbb49c617b1dac9c031dcf826259a08bdccbd914 /driver/tcpm/ps8xxx.h | |
| parent | 1da01c3a7a5d57bf3618deba20e424ae409f7d6c (diff) | |
| download | chrome-ec-ce1a0c9bdfa0b35455b9619fdb1b5794caa63894.tar.gz | |
ps8xxx: disable DCI mode
DCI mode is auto-enabled by default. we don't actually support DCI
(intel specific SoC debug path), so we can explicitly disable DCI
mode. doing so, saves about 40mW on the 3.3v rail when USB2 devices
or USB-C to USB-A dongles are left plugged in. this is particulary
relevant in sleep mode as this accounts for a significant portion
of the system power consumption.
BUG=b:119875949
BRANCH=none
TEST=verified power consumption drops using sweetberry, USB devices
still functional across suspend/resume.
Change-Id: Id13630425c78965d2ac4f2e97715374ae0640d23
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1732231
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Caveh Jalali <caveh@google.com>
Diffstat (limited to 'driver/tcpm/ps8xxx.h')
| -rw-r--r-- | driver/tcpm/ps8xxx.h | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index b94156652d..e2927c8531 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -9,10 +9,11 @@ #define __CROS_EC_USB_PD_TCPM_PS8XXX_H /* I2C interface */ -#define PS8751_I2C_ADDR1_FLAGS 0x0B -#define PS8751_I2C_ADDR2_FLAGS 0x1B -#define PS8751_I2C_ADDR3_FLAGS 0x2B -#define PS8751_I2C_ADDR4_FLAGS 0x4B +#define PS8751_I2C_ADDR1_P1_FLAGS 0x09 +#define PS8751_I2C_ADDR1_FLAGS 0x0B +#define PS8751_I2C_ADDR2_FLAGS 0x1B +#define PS8751_I2C_ADDR3_FLAGS 0x2B +#define PS8751_I2C_ADDR4_FLAGS 0x4B /* Minimum Delay for reset assertion */ #define PS8XXX_RESET_DELAY_MS 1 @@ -29,12 +30,17 @@ #define PS8XXX_VENDOR_ID 0x1DA0 #define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */ #define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC #define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD #define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE -#define PS8XXX_REG_BIST_CONT_MODE_CTR 0XBF +#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF #define PS8XXX_REG_DET_CTRL0 0x08 +#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0 +#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80 + #if defined(CONFIG_USB_PD_TCPM_PS8751) /* Vendor defined registers */ #define PS8XXX_PRODUCT_ID 0x8751 @@ -49,13 +55,15 @@ #define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4 #define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 #define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 +#define PS8751_REG_MUX_USB_DCI_CFG 0xED #elif defined(CONFIG_USB_PD_TCPM_PS8805) /* Vendor defined registers */ #define PS8XXX_PRODUCT_ID 0x8805 -#define FW_VER_REG 0x82 -#define MUX_IN_HPD_ASSERTION_REG 0xD0 +#define PS8805_P1_REG_MUX_USB_DCI_CFG 0x4B +#define FW_VER_REG 0x82 +#define MUX_IN_HPD_ASSERTION_REG 0xD0 #define IN_HPD BIT(0) #define HPD_IRQ BIT(1) |