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| author | Diana Z <dzigterman@chromium.org> | 2021-01-28 15:43:57 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-29 01:13:34 +0000 |
| commit | 99a13454b649a98d271014eb201f0149f3474c0b (patch) | |
| tree | ef8ed738ea6c743b7d8742919f30a75b213c8c30 /driver/tcpm/raa489000.h | |
| parent | e05473b236bb953788f77589907da9731f8d00ca (diff) | |
| download | chrome-ec-99a13454b649a98d271014eb201f0149f3474c0b.tar.gz | |
RAA489000: Organize header file
Put register definitions in ascending order and note some definitions
are no longer applicable.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ic840a59fafbf2fc711900103118d6ac7361ab249
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2658375
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'driver/tcpm/raa489000.h')
| -rw-r--r-- | driver/tcpm/raa489000.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h index 89cd4ff5a6..48bfa7c45a 100644 --- a/driver/tcpm/raa489000.h +++ b/driver/tcpm/raa489000.h @@ -16,18 +16,25 @@ #define RAA489000_TCPC3_I2C_FLAGS 0x25 /* Vendor registers */ -#define RAA489000_TCPC_SETTING1 0x80 -#define RAA489000_TYPEC_SETTING1 0xC0 -#define RAA489000_PD_PHYSICAL_SETTING1 0xE0 -#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8 +#define RAA489000_TCPC_SETTING1 0x80 +#define RAA489000_VBUS_CURRENT_TARGET 0x92 +#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94 +#define RAA489000_TYPEC_SETTING1 0xC0 +#define RAA489000_PD_PHYSICAL_SETTING1 0xE0 +#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8 -#define RAA489000_VBUS_CURRENT_TARGET 0x92 -#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94 +/* TCPC_SETTING_1 */ +#define RAA489000_TCPCV1_0_EN BIT(0) +#define RAA489000_TCPC_PWR_CNTRL BIT(4) +/* VBUS_CURRENT_TARGET */ #define RAA489000_VBUS_CURRENT_TARGET_VALUE 0x61 /* 3.104A */ + +/* VBUS_OCP_UV_THRESHOLD */ /* Detect voltage level of overcurrent protection during Sourcing VBUS */ #define RAA489000_OCP_THRESHOLD_VALUE 0x00BE /* 4.75V */ +/* TYPEC_SETTING1 - only older silicon */ /* Enables for reverse current protection */ #define RAA489000_SETTING1_IP2_EN BIT(9) #define RAA489000_SETTING1_IP1_EN BIT(8) @@ -46,10 +53,6 @@ /* CC debounce enable */ #define RAA489000_SETTING1_CC_DB_EN BIT(0) -/* TCPC_SETTING_1 */ -#define RAA489000_TCPCV1_0_EN BIT(0) -#define RAA489000_TCPC_PWR_CNTRL BIT(4) - /* PD_PHYSICAL_SETTING_1 */ #define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9) #define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8) |