diff options
| author | Patryk Duda <pdk@semihalf.com> | 2021-02-08 15:11:12 +0100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-10 08:57:23 +0000 |
| commit | 69fd9b54fb2785ef0ff020c9b8cfaec9a5a412a9 (patch) | |
| tree | 671c683f8a69227afa4c4aa375f426535db408d6 /driver/tcpm/tusb422.h | |
| parent | ccf7e98b4176c80780a80f53b465d992e09ce68d (diff) | |
| download | chrome-ec-69fd9b54fb2785ef0ff020c9b8cfaec9a5a412a9.tar.gz | |
tusb422: Don't perform soft reset during initialization
After waking from Low Power Mode, TCPMv2 always performs TCPC
initialization. Issuing soft reset during initialization leads to
lose information about DRP result and set CC lines to Rd. When
attaching sink, TCPC will report that nothing is connected and as a
result TCPMv2 will enable DRP and go to Low Power Mode again.
When LPM debounce delay is longer than tDRP (time in which TCPC will
advertise source and sink, between 50ms and 100ms according to Type-C
specification), then TCPC will always find connection before going to
Low Power Mode. If it is smaller, TCPMv2 will loop between LowPowerMode
and DRPAutoToggle states.
BUG=b:176986511
BRANCH=none
TEST=Run EC on Volteer board. Check if TCPC works.
TEST=Change PD_LPM_DEBOUNCE_US to 10ms and check if sink (eg. pendrive)
is detected correctly.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I0cd56d9a9ca31239afb4e41302e98b7996fb3a47
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682482
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'driver/tcpm/tusb422.h')
| -rw-r--r-- | driver/tcpm/tusb422.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/driver/tcpm/tusb422.h b/driver/tcpm/tusb422.h index 3d2006b2c3..f39939b184 100644 --- a/driver/tcpm/tusb422.h +++ b/driver/tcpm/tusb422.h @@ -16,9 +16,6 @@ #define TUSB422_REG_VENDOR_INTERRUPTS_MASK 0x92 #define TUSB422_REG_VENDOR_INTERRUPTS_MASK_FRS_RX BIT(0) -#define TUSB422_REG_CC_GEN_CTRL 0x94 -#define TUSB422_REG_CC_GEN_CTRL_GLOBAL_SW_RST BIT(5) - #define TUSB422_REG_PHY_BMC_RX_CTRL 0x96 #define TUSB422_REG_PHY_BMC_RX_CTRL_FRS_RX_EN BIT(3) |