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author | Ting Shen <phoenixshen@google.com> | 2021-04-23 18:22:20 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-08-03 08:47:37 +0000 |
commit | 7f714b91bb02ecc9afeff4c0a4da65ea8294af31 (patch) | |
tree | d881a332f90cb7c7830a9486580ce4f11ad9e753 /driver/tcpm | |
parent | b690911962e0c0b73243f388209fa1c2d22e7d9d (diff) | |
download | chrome-ec-7f714b91bb02ecc9afeff4c0a4da65ea8294af31.tar.gz |
tcpm/rt1718s: implement software workaround
Implement the software workarounds suggested by Richtek.
See issue link for details.
BUG=b:194982205
TEST=On Cherry & Tomato, manually verify PD works
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I7d9c6c5fd3c9266f27e52c1756a7ecedc75f1846
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848280
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'driver/tcpm')
-rw-r--r-- | driver/tcpm/rt1718s.c | 47 | ||||
-rw-r--r-- | driver/tcpm/rt1718s.h | 18 |
2 files changed, 65 insertions, 0 deletions
diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c index ea5fd3229c..a2e05838de 100644 --- a/driver/tcpm/rt1718s.c +++ b/driver/tcpm/rt1718s.c @@ -155,6 +155,39 @@ static int rt1718s_bc12_init(int port) return EC_SUCCESS; } +static int rt1718s_workaround(int port) +{ + int device_id; + + RETURN_ERROR(tcpc_read16(port, RT1718S_DEVICE_ID, &device_id)); + + switch (device_id) { + case RT1718S_DEVICE_ID_ES1: + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3, + RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG, + 0xFF)); + /* fallthrough */ + case RT1718S_DEVICE_ID_ES2: + RETURN_ERROR(rt1718s_update_bits8(port, TCPC_REG_FAULT_CTRL, + TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS, + 0xFF)); + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4, + RT1718S_VCON_CTRL4_UVP_CP_EN | + RT1718S_VCON_CTRL4_OVP_CP_EN, + 0)); + RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_2, + RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 | + RT1718S_VCONN_CONTROL_2_OVP_EN_CC2, + 0xFF)); + break; + default: + /* do nothing */ + break; + } + + return EC_SUCCESS; +} + static int rt1718s_init(int port) { static bool need_sw_reset = true; @@ -194,6 +227,7 @@ static int rt1718s_init(int port) RETURN_ERROR(tcpci_tcpm_init(port)); + RETURN_ERROR(rt1718s_workaround(port)); /* * Set vendor defined alert unmasked, this must be done after * tcpci_tcpm_init. @@ -310,6 +344,19 @@ void rt1718s_vendor_defined_alert(int port) if (value & RT1718S_RT_INT6_INT_BC12_SNK_DONE) task_set_event(USB_CHG_PORT_TO_TASK_ID(port), USB_CHG_EVENT_BC12); + + /* clear the alerts from rt1718s_workaround() */ + rv = rt1718s_write8(port, RT1718S_RT_INT2, 0xFF); + if (rv) + return; + /* ES1 workaround: disable Vconn discharge */ + rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL2, + RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN, + 0); + if (rv) + return; + + tcpc_write16(port, TCPC_REG_ALERT, TCPC_REG_ALERT_VENDOR_DEF); } static void rt1718s_alert(int port) diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h index 23370f3f56..fd1547cf25 100644 --- a/driver/tcpm/rt1718s.h +++ b/driver/tcpm/rt1718s.h @@ -15,6 +15,10 @@ #define RT1718S_VID 0x29CF #define RT1718S_PID 0x1718 +#define RT1718S_DEVICE_ID 0x04 +#define RT1718S_DEVICE_ID_ES1 0x4511 +#define RT1718S_DEVICE_ID_ES2 0x4513 + #define RT1718S_PHYCTRL1 0x80 #define RT1718S_PHYCTRL2 0x81 #define RT1718S_PHYCTRL3 0x82 @@ -28,6 +32,15 @@ #define RT1718S_SYS_CTRL2_BMCIO_OSC_EN BIT(0) #define RT1718S_SYS_CTRL2_LPWR_EN BIT(3) +#define RT1718S_VCONN_CONTROL_2 0x8B +#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7) +#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6) +#define RT1718S_VCONN_CONTROL_3 0x8C +#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1) + +#define RT1718S_SYS_CTRL2 0x90 +#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN BIT(5) + #define RT1718S_RT_MASK1 0x91 #define RT1718S_RT_MASK1_M_VBUS_FRS_LOW BIT(7) #define RT1718S_RT_MASK1_M_RX_FRS BIT(6) @@ -41,6 +54,7 @@ #define RT1718S_RT_MASK6_M_BC12_TA_CHG BIT(5) #define RT1718S_RT_MASK7 0x97 +#define RT1718S_RT_INT2 0x99 #define RT1718S_RT_INT6 0x9D #define RT1718S_RT_INT6_INT_BC12_SNK_DONE BIT(7) #define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE BIT(6) @@ -89,6 +103,10 @@ #define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL (BIT(5) | BIT(4)) #define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL 0x0F +#define RT1718S_VCON_CTRL4 0xF211 +#define RT1718S_VCON_CTRL4_UVP_CP_EN BIT(5) +#define RT1718S_VCON_CTRL4_OVP_CP_EN BIT(4) + #define RT1718S_RT2_VBUS_OCRC_EN 0xF214 #define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN BIT(0) #define RT1718S_RT2_VBUS_OCP_CTRL1 0xF216 |