common: replace 1 << digits, with BIT(digits)

Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.

Fix an error in motion_lid try to set bit 31 of a signed integer.

BUG=None
BRANCH=None
TEST=compile

Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

9 files changed, 134 insertions, 134 deletions

diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c
index 3eac7732af..5b49cd685e 100644
--- a/driver/tcpm/anx7447.c
+++ b/driver/tcpm/anx7447.c
@@ -18,15 +18,15 @@
 #define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
 #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
 
-#define ANX7447_VENDOR_ALERT    (1 << 15)
+#define ANX7447_VENDOR_ALERT    BIT(15)
 
 #define ANX7447_REG_STATUS      0x82
-#define ANX7447_REG_STATUS_LINK (1 << 0)
+#define ANX7447_REG_STATUS_LINK BIT(0)
 
 #define ANX7447_REG_HPD         0x83
-#define ANX7447_REG_HPD_HIGH    (1 << 0)
-#define ANX7447_REG_HPD_IRQ     (1 << 1)
-#define ANX7447_REG_HPD_ENABLE  (1 << 2)
+#define ANX7447_REG_HPD_HIGH    BIT(0)
+#define ANX7447_REG_HPD_IRQ     BIT(1)
+#define ANX7447_REG_HPD_ENABLE  BIT(2)
 
 #define vsafe5v_min (3800/25)
 #define vsafe0v_max (800/25)
diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h
index deaebf3f1d..18708d38b4 100644
--- a/driver/tcpm/anx74xx.h
+++ b/driver/tcpm/anx74xx.h
@@ -30,16 +30,16 @@
 
 #define ANX74XX_REG_INTP_VCONN_CTRL	0x33
 #define ANX74XX_REG_VCONN_DISABLE		0x0f
-#define ANX74XX_REG_VCONN_1_ENABLE		(1 << 4)
-#define ANX74XX_REG_VCONN_2_ENABLE		(1 << 5)
-#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN	(1 << 2)
+#define ANX74XX_REG_VCONN_1_ENABLE		BIT(4)
+#define ANX74XX_REG_VCONN_2_ENABLE		BIT(5)
+#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN	BIT(2)
 
 #define ANX74XX_STANDBY_MODE		(0)
 #define ANX74XX_NORMAL_MODE		(1)
 
 #define ANX74XX_REG_TX_CTRL_1		0x81
-#define ANX74XX_REG_TX_HARD_RESET_REQ	(1 << 1)
-#define ANX74XX_REG_TX_CABLE_RESET_REQ	(1 << 2)
+#define ANX74XX_REG_TX_HARD_RESET_REQ	BIT(1)
+#define ANX74XX_REG_TX_CABLE_RESET_REQ	BIT(2)
 
 #define ANX74XX_REG_TX_CTRL_2		0x82
 #define ANX74XX_REG_TX_WR_FIFO		0x83
@@ -50,36 +50,36 @@
 #define ANX74XX_REG_TX_START_ADDR_1		0xd0
 
 #define ANX74XX_REG_CTRL_COMMAND		0xdb
-#define ANX74XX_REG_TX_SEND_DATA_REQ	(1 << 0)
-#define ANX74XX_REG_TX_HARD_RST_REQ	(1 << 1)
+#define ANX74XX_REG_TX_SEND_DATA_REQ	BIT(0)
+#define ANX74XX_REG_TX_HARD_RST_REQ	BIT(1)
 
 #define ANX74XX_REG_TX_BIST_CTRL 0x9D
-#define ANX74XX_REG_TX_BIST_MODE (1 << 4)
-#define ANX74XX_REG_TX_BIST_STOP (1 << 3)
-#define ANX74XX_REG_TX_BIXT_FOREVER (1 << 2)
-#define ANX74XX_REG_TX_BIST_ENABLE (1 << 1)
-#define ANX74XX_REG_TX_BIST_START (1 << 0)
+#define ANX74XX_REG_TX_BIST_MODE BIT(4)
+#define ANX74XX_REG_TX_BIST_STOP BIT(3)
+#define ANX74XX_REG_TX_BIXT_FOREVER BIT(2)
+#define ANX74XX_REG_TX_BIST_ENABLE BIT(1)
+#define ANX74XX_REG_TX_BIST_START BIT(0)
 
 #define ANX74XX_REG_PD_HEADER		0x69
 #define ANX74XX_REG_PD_RX_DATA_OBJ		0x11
 #define ANX74XX_REG_PD_RX_DATA_OBJ_M	0x4d
 
 #define ANX74XX_REG_ANALOG_STATUS		0x40
-#define ANX74XX_REG_VBUS_STATUS		(1 << 4)
+#define ANX74XX_REG_VBUS_STATUS		BIT(4)
 #define ANX74XX_REG_CC_PULL_RD		0xfd
 #define ANX74XX_REG_CC_PULL_RP		0x02
 
 
 #define ANX74XX_REG_TX_AUTO_GOODCRC_2	0x94
-#define ANX74XX_REG_REPLY_SOP_EN        (1 << 3)
-#define ANX74XX_REG_REPLY_SOP_1_EN      (1 << 4)
-#define ANX74XX_REG_REPLY_SOP_2_EN      (1 << 5)
+#define ANX74XX_REG_REPLY_SOP_EN        BIT(3)
+#define ANX74XX_REG_REPLY_SOP_1_EN      BIT(4)
+#define ANX74XX_REG_REPLY_SOP_2_EN      BIT(5)
 
 #define ANX74XX_REG_TX_AUTO_GOODCRC_1	0x9c
 #define ANX74XX_REG_SPEC_REV_BIT_POS	(3)
 #define ANX74XX_REG_DATA_ROLE_BIT_POS	(2)
 #define ANX74XX_REG_PWR_ROLE_BIT_POS	(1)
-#define ANX74XX_REG_AUTO_GOODCRC_EN	(1 << 0)
+#define ANX74XX_REG_AUTO_GOODCRC_EN	BIT(0)
 #define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole)    \
 	((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \
 	((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS)  | \
@@ -88,7 +88,7 @@
 
 
 #define ANX74XX_REG_ANALOG_CTRL_0		0x41
-#define ANX74XX_REG_R_PIN_CABLE_DET		(1 << 7)
+#define ANX74XX_REG_R_PIN_CABLE_DET		BIT(7)
 
 #define ANX74XX_REG_ANALOG_CTRL_1		0x42
 #define ANX74XX_REG_ANALOG_CTRL_5		0x46
@@ -106,19 +106,19 @@
 #define ANX74XX_REG_ANALOG_CTRL_11		0x4c
 #define ANX74XX_REG_ANALOG_CTRL_12		0x4d
 
-#define ANX74XX_REG_MUX_ML0_RX2		(1 << 0)
-#define ANX74XX_REG_MUX_ML0_RX1		(1 << 1)
-#define ANX74XX_REG_MUX_ML3_RX2		(1 << 2)
-#define ANX74XX_REG_MUX_ML3_RX1		(1 << 3)
-#define ANX74XX_REG_MUX_SSRX_RX2	(1 << 4)
-#define ANX74XX_REG_MUX_SSRX_RX1	(1 << 5)
-#define ANX74XX_REG_MUX_ML1_TX2		(1 << 6)
-#define ANX74XX_REG_MUX_ML1_TX1		(1 << 7)
+#define ANX74XX_REG_MUX_ML0_RX2		BIT(0)
+#define ANX74XX_REG_MUX_ML0_RX1		BIT(1)
+#define ANX74XX_REG_MUX_ML3_RX2		BIT(2)
+#define ANX74XX_REG_MUX_ML3_RX1		BIT(3)
+#define ANX74XX_REG_MUX_SSRX_RX2	BIT(4)
+#define ANX74XX_REG_MUX_SSRX_RX1	BIT(5)
+#define ANX74XX_REG_MUX_ML1_TX2		BIT(6)
+#define ANX74XX_REG_MUX_ML1_TX1		BIT(7)
 
-#define ANX74XX_REG_MUX_ML2_TX2		(1 << 4)
-#define ANX74XX_REG_MUX_ML2_TX1		(1 << 5)
-#define ANX74XX_REG_MUX_SSTX_TX2	(1 << 6)
-#define ANX74XX_REG_MUX_SSTX_TX1	(1 << 7)
+#define ANX74XX_REG_MUX_ML2_TX2		BIT(4)
+#define ANX74XX_REG_MUX_ML2_TX1		BIT(5)
+#define ANX74XX_REG_MUX_SSTX_TX2	BIT(6)
+#define ANX74XX_REG_MUX_SSTX_TX1	BIT(7)
 
 #define ANX74XX_REG_CC_SOFTWARE_CTRL	0x4a
 #define ANX74XX_REG_CC_SW_CTRL_ENABLE	0x01
@@ -133,29 +133,29 @@
 #define ANX74XX_REG_IRQ_EXT_MASK_1		0x3b
 #define ANX74XX_REG_IRQ_EXT_MASK_2		0x3c
 #define ANX74XX_REG_IRQ_EXT_SOURCE_1	0x3e
-#define ANX74XX_REG_EXT_SOP                     (1 << 6)
-#define ANX74XX_REG_EXT_SOP_PRIME               (1 << 7)
+#define ANX74XX_REG_EXT_SOP                     BIT(6)
+#define ANX74XX_REG_EXT_SOP_PRIME               BIT(7)
 #define ANX74XX_REG_IRQ_EXT_SOURCE_2	0x4e
-#define ANX74XX_REG_EXT_SOP_PRIME_PRIME         (1 << 0)
-#define ANX74XX_REG_EXT_HARD_RST		(1 << 2)
+#define ANX74XX_REG_EXT_SOP_PRIME_PRIME         BIT(0)
+#define ANX74XX_REG_EXT_HARD_RST		BIT(2)
 #define ANX74XX_REG_IRQ_EXT_SOURCE_3	0x4f
-#define ANX74XX_REG_CLEAR_SOFT_IRQ		(1 << 2)
+#define ANX74XX_REG_CLEAR_SOFT_IRQ		BIT(2)
 
 #define ANX74XX_REG_IRQ_SOURCE_RECV_MSG	0x6b
-#define ANX74XX_REG_IRQ_CC_MSG_INT		(1 << 0)
-#define ANX74XX_REG_IRQ_CC_STATUS_INT	(1 << 1)
-#define ANX74XX_REG_IRQ_GOOD_CRC_INT	(1 << 2)
-#define ANX74XX_REG_IRQ_TX_FAIL_INT	(1 << 3)
+#define ANX74XX_REG_IRQ_CC_MSG_INT		BIT(0)
+#define ANX74XX_REG_IRQ_CC_STATUS_INT	BIT(1)
+#define ANX74XX_REG_IRQ_GOOD_CRC_INT	BIT(2)
+#define ANX74XX_REG_IRQ_TX_FAIL_INT	BIT(3)
 #define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK	0x6c
 
 #define ANX74XX_REG_CLEAR_SET_BITS		0xff
-#define ANX74XX_REG_ALERT_HARD_RST_RECV		(1 << 6)
-#define ANX74XX_REG_ALERT_MSG_RECV		(1 << 5)
-#define ANX74XX_REG_ALERT_TX_MSG_ERROR	(1 << 4)
-#define ANX74XX_REG_ALERT_TX_ACK_RECV	(1 << 3)
-#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK	(1 << 2)
-#define ANX74XX_REG_ALERT_TX_HARD_RESETOK	(1 << 1)
-#define ANX74XX_REG_ALERT_CC_CHANGE	(1 << 0)
+#define ANX74XX_REG_ALERT_HARD_RST_RECV		BIT(6)
+#define ANX74XX_REG_ALERT_MSG_RECV		BIT(5)
+#define ANX74XX_REG_ALERT_TX_MSG_ERROR	BIT(4)
+#define ANX74XX_REG_ALERT_TX_ACK_RECV	BIT(3)
+#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK	BIT(2)
+#define ANX74XX_REG_ALERT_TX_HARD_RESETOK	BIT(1)
+#define ANX74XX_REG_ALERT_CC_CHANGE	BIT(0)
 
 #define ANX74XX_REG_ANALOG_CTRL_2		0x43
 #define ANX74XX_REG_MODE_TRANS		0x01
@@ -181,12 +181,12 @@
 #define ANX74XX_REG_CTRL_FW  0x2E
 #define CLEAR_RX_BUFFER (1)
 #define ANX74XX_REG_POWER_DOWN_CTRL	0x0d
-#define ANX74XX_REG_STATUS_CC1_VRD_USB	(1 << 7)
-#define ANX74XX_REG_STATUS_CC1_VRD_1P5	(1 << 6)
-#define ANX74XX_REG_STATUS_CC1_VRD_3P0	(1 << 5)
-#define ANX74XX_REG_STATUS_CC2_VRD_USB	(1 << 4)
-#define ANX74XX_REG_STATUS_CC2_VRD_1P5	(1 << 3)
-#define ANX74XX_REG_STATUS_CC2_VRD_3P0	(1 << 2)
+#define ANX74XX_REG_STATUS_CC1_VRD_USB	BIT(7)
+#define ANX74XX_REG_STATUS_CC1_VRD_1P5	BIT(6)
+#define ANX74XX_REG_STATUS_CC1_VRD_3P0	BIT(5)
+#define ANX74XX_REG_STATUS_CC2_VRD_USB	BIT(4)
+#define ANX74XX_REG_STATUS_CC2_VRD_1P5	BIT(3)
+#define ANX74XX_REG_STATUS_CC2_VRD_3P0	BIT(2)
 
 /* defined in the inter-bock Spec: 4.2.10 CC Detect Status */
 #define ANX74XX_REG_CC_STATUS_MASK  0xf
diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c
index c9d6045b44..bac65892de 100644
--- a/driver/tcpm/anx7688.c
+++ b/driver/tcpm/anx7688.c
@@ -11,19 +11,19 @@
 #include "timer.h"
 #include "usb_mux.h"
 
-#define ANX7688_VENDOR_ALERT    (1 << 15)
+#define ANX7688_VENDOR_ALERT    BIT(15)
 
 #define ANX7688_REG_STATUS      0x82
-#define ANX7688_REG_STATUS_LINK (1 << 0)
+#define ANX7688_REG_STATUS_LINK BIT(0)
 
 #define ANX7688_REG_HPD         0x83
-#define ANX7688_REG_HPD_HIGH    (1 << 0)
-#define ANX7688_REG_HPD_IRQ     (1 << 1)
-#define ANX7688_REG_HPD_ENABLE  (1 << 2)
+#define ANX7688_REG_HPD_HIGH    BIT(0)
+#define ANX7688_REG_HPD_IRQ     BIT(1)
+#define ANX7688_REG_HPD_ENABLE  BIT(2)
 
 #define ANX7688_USBC_ADDR		0x50
 #define ANX7688_REG_RAMCTRL		0xe7
-#define ANX7688_REG_RAMCTRL_BOOT_DONE	(1 << 6)
+#define ANX7688_REG_RAMCTRL_BOOT_DONE	BIT(6)
 
 static int anx7688_init(int port)
 {
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c
index f63e9e38bb..b31a9192f7 100644
--- a/driver/tcpm/it83xx.c
+++ b/driver/tcpm/it83xx.c
@@ -45,7 +45,7 @@ void it83xx_disable_pd_module(int port)
 	if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG &&
 		*usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) {
 		/* Disable PD PHY */
-		IT83XX_USBPD_GCR(port) &= ~((1 << 0) | (1 << 4));
+		IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4));
 		/* Power down CC1/CC2 */
 		IT83XX_USBPD_CCGCR(port) |= 0x1f;
 		/* Disable CC1/CC2 voltage detector */
@@ -70,10 +70,10 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 
 	/* select Rp */
 	if (pull)
-		CLEAR_MASK(cc_state, (1 << 2));
+		CLEAR_MASK(cc_state, BIT(2));
 	/* select Rd */
 	else
-		SET_MASK(cc_state, (1 << 2));
+		SET_MASK(cc_state, BIT(2));
 
 	/* sink */
 	if (USBPD_GET_POWER_ROLE(port) == USBPD_POWER_ROLE_CONSUMER) {
@@ -181,7 +181,7 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 
 	if (length) {
 		/* set data bit */
-		IT83XX_USBPD_MTSR0(port) |= (1 << 4);
+		IT83XX_USBPD_MTSR0(port) |= BIT(4);
 		/* set data length setting */
 		IT83XX_USBPD_MTSR1(port) |= length;
 		/* set data */
@@ -279,9 +279,9 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
 static void it83xx_enable_cc(enum usbpd_port port, int enable)
 {
 	if (enable)
-		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 4));
+		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(4));
 	else
-		SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 4));
+		SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(4));
 }
 
 static void it83xx_set_power_role(enum usbpd_port port, int power_role)
@@ -300,11 +300,11 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role)
 		 */
 		IT83XX_USBPD_CCADCR(port) = 0x08;
 		/* bit0: source */
-		SET_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0));
+		SET_MASK(IT83XX_USBPD_PDMSR(port), BIT(0));
 		/* bit1: CC1 select Rp */
-		SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 1));
+		SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(1));
 		/* bit3: CC2 select Rp */
-		SET_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3));
+		SET_MASK(IT83XX_USBPD_BMCSR(port), BIT(3));
 	} else {
 		/*
 		 * bit[2,3] BMC Rx threshold setting
@@ -318,11 +318,11 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role)
 		 */
 		IT83XX_USBPD_CCADCR(port) = 0x04;
 		/* bit0: sink */
-		CLEAR_MASK(IT83XX_USBPD_PDMSR(port), (1 << 0));
+		CLEAR_MASK(IT83XX_USBPD_PDMSR(port), BIT(0));
 		/* bit1: CC1 select Rd */
-		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 1));
+		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(1));
 		/* bit3: CC2 select Rd */
-		CLEAR_MASK(IT83XX_USBPD_BMCSR(port), (1 << 3));
+		CLEAR_MASK(IT83XX_USBPD_BMCSR(port), BIT(3));
 	}
 }
 
@@ -339,10 +339,10 @@ static void it83xx_init(enum usbpd_port port, int role)
 	invalidate_last_message_id(port);
 #ifdef IT83XX_USBPD_CC_PARAMETER_RELOAD
 	/* bit7: Reload CC parameter setting. */
-	IT83XX_USBPD_CCPSR0(port) |= (1 << 7);
+	IT83XX_USBPD_CCPSR0(port) |= BIT(7);
 #endif
 	/* reset and disable HW auto generate message header */
-	IT83XX_USBPD_GCR(port) = (1 << 5);
+	IT83XX_USBPD_GCR(port) = BIT(5);
 	USBPD_SW_RESET(port);
 	/* set SOP: receive SOP message only.
 	 * bit[7]: SOP" support enable.
@@ -379,7 +379,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 	/* disable vconn */
 	it83xx_enable_vconn(port, 0);
 	/* TX start from high */
-	IT83XX_USBPD_CCADCR(port) |= (1 << 6);
+	IT83XX_USBPD_CCADCR(port) |= BIT(6);
 	/* enable cc1/cc2 */
 	*usbpd_ctrl_regs[port].cc1 = IT83XX_USBPD_CC_PIN_CONFIG;
 	*usbpd_ctrl_regs[port].cc2 = IT83XX_USBPD_CC_PIN_CONFIG;
@@ -393,9 +393,9 @@ static void it83xx_select_polarity(enum usbpd_port port,
 {
 	/* cc1/cc2 selection */
 	if (cc_pin == USBPD_CC_PIN_1)
-		SET_MASK(IT83XX_USBPD_CCGCR(port), (1 << 0));
+		SET_MASK(IT83XX_USBPD_CCGCR(port), BIT(0));
 	else
-		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), (1 << 0));
+		CLEAR_MASK(IT83XX_USBPD_CCGCR(port), BIT(0));
 }
 
 static int it83xx_set_cc(enum usbpd_port port, int pull)
@@ -457,7 +457,7 @@ static int it83xx_tcpm_select_rp_value(int port, int rp_sel)
 		rp = 2 << 2;
 		break;
 	case TYPEC_RP_3A0:
-		rp = 1 << 2;
+		rp = BIT(2);
 		break;
 	case TYPEC_RP_USB:
 	default:
diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h
index 0f6be9b24f..73c613ff0e 100644
--- a/driver/tcpm/it83xx_pd.h
+++ b/driver/tcpm/it83xx_pd.h
@@ -14,7 +14,7 @@
  */
 #define IT83XX_USBPD_CC_PIN_CONFIG 0x86
 
-#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM((1 << 17))
+#define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM(BIT(17))
 
 #define SET_MASK(reg, bit_mask)      ((reg) |= (bit_mask))
 #define CLEAR_MASK(reg, bit_mask)    ((reg) &= (~(bit_mask)))
@@ -51,9 +51,9 @@
 #define USBPD_GET_POWER_ROLE(port)                  \
 	(IT83XX_USBPD_PDMSR(port) & 1)
 #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
-	(IT83XX_USBPD_CCGCR(port) & (1 << 1))
+	(IT83XX_USBPD_CCGCR(port) & BIT(1))
 #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
-	(IT83XX_USBPD_BMCSR(port) & (1 << 3))
+	(IT83XX_USBPD_BMCSR(port) & BIT(3))
 #define USBPD_GET_PULL_CC_SELECTION(port)           \
 	(IT83XX_USBPD_CCGCR(port) & 1)
 
diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h
index 5fdcffbdca..1d30d27f8f 100644
--- a/driver/tcpm/mt6370.h
+++ b/driver/tcpm/mt6370.h
@@ -63,45 +63,45 @@
  * MT6370_REG_CLK_CTRL2				0x87
  */
 
-#define MT6370_REG_CLK_DIV_600K_EN		(1 << 7)
-#define MT6370_REG_CLK_BCLK2_EN			(1 << 6)
-#define MT6370_REG_CLK_BCLK2_TG_EN		(1 << 5)
-#define MT6370_REG_CLK_DIV_300K_EN		(1 << 3)
-#define MT6370_REG_CLK_CK_300K_EN		(1 << 2)
-#define MT6370_REG_CLK_BCLK_EN			(1 << 1)
-#define MT6370_REG_CLK_BCLK_TH_EN		(1 << 0)
+#define MT6370_REG_CLK_DIV_600K_EN		BIT(7)
+#define MT6370_REG_CLK_BCLK2_EN			BIT(6)
+#define MT6370_REG_CLK_BCLK2_TG_EN		BIT(5)
+#define MT6370_REG_CLK_DIV_300K_EN		BIT(3)
+#define MT6370_REG_CLK_CK_300K_EN		BIT(2)
+#define MT6370_REG_CLK_BCLK_EN			BIT(1)
+#define MT6370_REG_CLK_BCLK_TH_EN		BIT(0)
 
 /*
  * MT6370_REG_CLK_CTRL3				0x88
  */
 
-#define MT6370_REG_CLK_OSCMUX_RG_EN		(1 << 7)
-#define MT6370_REG_CLK_CK_24M_EN		(1 << 6)
-#define MT6370_REG_CLK_OSC_RG_EN		(1 << 5)
-#define MT6370_REG_CLK_DIV_2P4M_EN		(1 << 4)
-#define MT6370_REG_CLK_CK_2P4M_EN		(1 << 3)
-#define MT6370_REG_CLK_PCLK_EN			(1 << 2)
-#define MT6370_REG_CLK_PCLK_RG_EN		(1 << 1)
-#define MT6370_REG_CLK_PCLK_TG_EN		(1 << 0)
+#define MT6370_REG_CLK_OSCMUX_RG_EN		BIT(7)
+#define MT6370_REG_CLK_CK_24M_EN		BIT(6)
+#define MT6370_REG_CLK_OSC_RG_EN		BIT(5)
+#define MT6370_REG_CLK_DIV_2P4M_EN		BIT(4)
+#define MT6370_REG_CLK_CK_2P4M_EN		BIT(3)
+#define MT6370_REG_CLK_PCLK_EN			BIT(2)
+#define MT6370_REG_CLK_PCLK_RG_EN		BIT(1)
+#define MT6370_REG_CLK_PCLK_TG_EN		BIT(0)
 
 /*
  * MT6370_REG_RX_TX_DBG				0x8b
  */
 
-#define MT6370_REG_RX_TX_DBG_RX_BUSY		(1 << 7)
-#define MT6370_REG_RX_TX_DBG_TX_BUSY		(1 << 6)
+#define MT6370_REG_RX_TX_DBG_RX_BUSY		BIT(7)
+#define MT6370_REG_RX_TX_DBG_TX_BUSY		BIT(6)
 
 /*
  * MT6370_REG_BMC_CTRL				0x90
  */
 
-#define MT6370_REG_IDLE_EN			(1 << 6)
-#define MT6370_REG_DISCHARGE_EN			(1 << 5)
-#define MT6370_REG_BMCIO_LPRPRD			(1 << 4)
-#define MT6370_REG_BMCIO_LPEN			(1 << 3)
-#define MT6370_REG_BMCIO_BG_EN			(1 << 2)
-#define MT6370_REG_VBUS_DET_EN			(1 << 1)
-#define MT6370_REG_BMCIO_OSC_EN			(1 << 0)
+#define MT6370_REG_IDLE_EN			BIT(6)
+#define MT6370_REG_DISCHARGE_EN			BIT(5)
+#define MT6370_REG_BMCIO_LPRPRD			BIT(4)
+#define MT6370_REG_BMCIO_LPEN			BIT(3)
+#define MT6370_REG_BMCIO_BG_EN			BIT(2)
+#define MT6370_REG_VBUS_DET_EN			BIT(1)
+#define MT6370_REG_BMCIO_OSC_EN			BIT(0)
 #define MT6370_REG_BMC_CTRL_DEFAULT                                            \
 	(MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN |                     \
 	 MT6370_REG_BMCIO_OSC_EN)
@@ -111,41 +111,41 @@
  */
 
 #define MT6370_MASK_DISCHARGE_LVL		0x03
-#define MT6370_REG_DISCHARGE_LVL		(1 << 0)
+#define MT6370_REG_DISCHARGE_LVL		BIT(0)
 
 /*
  * MT6370_REG_RT_STATUS				0x97
  */
 
-#define MT6370_REG_RA_DETACH			(1 << 5)
-#define MT6370_REG_VBUS_80			(1 << 1)
+#define MT6370_REG_RA_DETACH			BIT(5)
+#define MT6370_REG_VBUS_80			BIT(1)
 
 /*
  * MT6370_REG_RT_INT				0x98
  */
 
-#define MT6370_REG_INT_RA_DETACH		(1 << 5)
-#define MT6370_REG_INT_WATCHDOG			(1 << 2)
-#define MT6370_REG_INT_VBUS_80			(1 << 1)
-#define MT6370_REG_INT_WAKEUP			(1 << 0)
+#define MT6370_REG_INT_RA_DETACH		BIT(5)
+#define MT6370_REG_INT_WATCHDOG			BIT(2)
+#define MT6370_REG_INT_VBUS_80			BIT(1)
+#define MT6370_REG_INT_WAKEUP			BIT(0)
 
 /*
  * MT6370_REG_RT_MASK				0x99
  */
 
-#define MT6370_REG_M_RA_DETACH			(1 << 5)
-#define MT6370_REG_M_WATCHDOG			(1 << 2)
-#define MT6370_REG_M_VBUS_80			(1 << 1)
-#define MT6370_REG_M_WAKEUP			(1 << 0)
+#define MT6370_REG_M_RA_DETACH			BIT(5)
+#define MT6370_REG_M_WATCHDOG			BIT(2)
+#define MT6370_REG_M_VBUS_80			BIT(1)
+#define MT6370_REG_M_WAKEUP			BIT(0)
 
 /*
  * MT6370_REG_IDLE_CTRL				0x9B
  */
 
-#define MT6370_REG_CK_300K_SEL			(1 << 7)
-#define MT6370_REG_SHIPPING_OFF			(1 << 5)
-#define MT6370_REG_ENEXTMSG			(1 << 4)
-#define MT6370_REG_AUTOIDLE_EN			(1 << 3)
+#define MT6370_REG_CK_300K_SEL			BIT(7)
+#define MT6370_REG_SHIPPING_OFF			BIT(5)
+#define MT6370_REG_ENEXTMSG			BIT(4)
+#define MT6370_REG_AUTOIDLE_EN			BIT(3)
 
 /* timeout = (tout*2+1) * 6.4ms */
 #ifdef CONFIG_USB_PD_REV30
@@ -161,7 +161,7 @@
  * MT6370_REG_INTRST_CTRL			0x9C
  */
 
-#define MT6370_REG_INTRST_EN			(1 << 7)
+#define MT6370_REG_INTRST_EN			BIT(7)
 
 /* timeout = (tout+1) * 0.2sec */
 #define MT6370_REG_INTRST_SET(en, tout)		((en << 7) | (tout & 0x03))
@@ -170,7 +170,7 @@
  * MT6370_REG_WATCHDOG_CTRL			0x9D
  */
 
-#define MT6370_REG_WATCHDOG_EN			(1 << 7)
+#define MT6370_REG_WATCHDOG_EN			BIT(7)
 
 /* timeout = (tout+1) * 0.4sec */
 #define MT6370_REG_WATCHDOG_CTRL_SET(en, tout)	((en << 7) | (tout & 0x07))
@@ -179,7 +179,7 @@
  * MT6370_REG_I2CRST_CTRL			0x9E
  */
 
-#define MT6370_REG_I2CRST_EN			(1 << 7)
+#define MT6370_REG_I2CRST_EN			BIT(7)
 
 /* timeout = (tout+1) * 12.5ms */
 #define MT6370_REG_I2CRST_SET(en, tout)		((en << 7) | (tout & 0x0f))
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h
index 6d0faab56f..6b94b56094 100644
--- a/driver/tcpm/ps8xxx.h
+++ b/driver/tcpm/ps8xxx.h
@@ -43,8 +43,8 @@
 #define PS8XXX_REG_VENDOR_ID_L                  0x00
 #define PS8XXX_REG_VENDOR_ID_H                  0x01
 #define MUX_IN_HPD_ASSERTION_REG                0xD0
-#define IN_HPD  (1 << 0)
-#define HPD_IRQ (1 << 1)
+#define IN_HPD  BIT(0)
+#define HPD_IRQ BIT(1)
 #define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION      0xD3
 #define PS8XXX_REG_MUX_USB_C2SS_EQ              0xE7
 #define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD    0xE8
@@ -55,8 +55,8 @@
 
 #define FW_VER_REG               0x82
 #define MUX_IN_HPD_ASSERTION_REG 0xD0
-#define IN_HPD  (1 << 0)
-#define HPD_IRQ (1 << 1)
+#define IN_HPD  BIT(0)
+#define HPD_IRQ BIT(1)
 
 #endif
 
diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c
index f20fbd91e3..59393a62a9 100644
--- a/driver/tcpm/tcpci.c
+++ b/driver/tcpm/tcpci.c
@@ -420,7 +420,7 @@ struct cached_tcpm_message {
 };
 
 /* Cache depth needs to be power of 2 */
-#define CACHE_DEPTH (1 << 2)
+#define CACHE_DEPTH BIT(2)
 #define CACHE_DEPTH_MASK (CACHE_DEPTH - 1)
 
 struct queue {
diff --git a/driver/tcpm/tcpci.h b/driver/tcpm/tcpci.h
index 8084e92232..600e28f284 100644
--- a/driver/tcpm/tcpci.h
+++ b/driver/tcpm/tcpci.h
@@ -43,9 +43,9 @@
 
 #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK          (3 << 2)
 #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE          (0 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB           (1 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB           BIT(2)
 #define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP            (2 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED (1 << 0)
+#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
 
 #define TCPC_REG_TCPC_CTRL         0x19
 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity)
@@ -62,7 +62,7 @@
 
 #define TCPC_REG_FAULT_CTRL        0x1b
 #define TCPC_REG_POWER_CTRL        0x1c
-#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE  (1 << 2)
+#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE  BIT(2)
 #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn)
 #define TCPC_REG_POWER_CTRL_VCONN(reg)    ((reg) & 0x1)