diff options
| author | Wai-Hong Tam <waihong@google.com> | 2018-10-15 14:38:35 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-02-01 15:19:41 -0800 |
| commit | 2a7b38e425279ff309eb94a71311d2a1ebfc29ee (patch) | |
| tree | 8ffe2438a25f4a8213fad52ad15cd8ef42b69f3c /driver/tcpm | |
| parent | 3f8e5056ba275d4f8c4596e5d5aa20e27dfb7e18 (diff) | |
| download | chrome-ec-2a7b38e425279ff309eb94a71311d2a1ebfc29ee.tar.gz | |
anx74xx: Make ML0/ML1 unconnected if USB is enabled but DP isn't
If USB is enabled, the original logic uses the pin assignment D
which also connects the ML0 and ML1 switches, not matter DP is
enabled or not. It affects some DP signal integrity on the other
port which shares the same DP source. Should make the ML0/ML1
switches unconnected if DP is not enabled.
BRANCH=none
BUG=b:116879483
TEST=According to the bug, manually typing the i2c command like this
change to disconnect ML0/ML1 fixes the issue.
Change-Id: Icfa10b97331be7935bb626771b41eb509fa61f50
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1282005
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Diffstat (limited to 'driver/tcpm')
| -rw-r--r-- | driver/tcpm/anx74xx.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/driver/tcpm/anx74xx.c b/driver/tcpm/anx74xx.c index 30438775b3..248887be28 100644 --- a/driver/tcpm/anx74xx.c +++ b/driver/tcpm/anx74xx.c @@ -393,18 +393,24 @@ static int anx74xx_tcpm_mux_set(int i2c_addr, mux_state_t mux_state) ctrl5 &= 0x0f; if (mux_state & MUX_USB_ENABLED) { - /* Set pin assignment D */ + /* Connect USB SS switches */ if (mux_state & MUX_POLARITY_INVERTED) { - ctrl1 = (ANX74XX_REG_MUX_ML0_RX1 | - ANX74XX_REG_MUX_ML1_TX1 | - ANX74XX_REG_MUX_SSRX_RX2); + ctrl1 = ANX74XX_REG_MUX_SSRX_RX2; ctrl5 |= ANX74XX_REG_MUX_SSTX_TX2; } else { - ctrl1 = (ANX74XX_REG_MUX_ML0_RX2 | - ANX74XX_REG_MUX_ML1_TX2 | - ANX74XX_REG_MUX_SSRX_RX1); + ctrl1 = ANX74XX_REG_MUX_SSRX_RX1; ctrl5 |= ANX74XX_REG_MUX_SSTX_TX1; } + if (mux_state & MUX_DP_ENABLED) { + /* Set pin assignment D */ + if (mux_state & MUX_POLARITY_INVERTED) + ctrl1 |= (ANX74XX_REG_MUX_ML0_RX1 | + ANX74XX_REG_MUX_ML1_TX1); + else + ctrl1 |= (ANX74XX_REG_MUX_ML0_RX2 | + ANX74XX_REG_MUX_ML1_TX2); + } + /* Keep ML0/ML1 unconnected if DP is not enabled */ } else if (mux_state & MUX_DP_ENABLED) { /* Set pin assignment C */ if (mux_state & MUX_POLARITY_INVERTED) { |