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| author | Aseda Aboagye <aaboagye@google.com> | 2020-02-14 12:28:59 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-18 20:19:23 +0000 |
| commit | 91e799554fcfb75f16188186866d042e1754f52e (patch) | |
| tree | 2794bac0bd2e20572e058b4a9478d4145ca54c02 /driver | |
| parent | b6adca6689753bdbe798cd1e0a56f8a4df749445 (diff) | |
| download | chrome-ec-91e799554fcfb75f16188186866d042e1754f52e.tar.gz | |
raa489000: Allow TCPC to control VBUS
In order to use the TCPCI interface to source VBUS, we need to allow the
TCPC to actually source VBUS. This commit simply sets that setting in
the TCPC.
BUG=b:149580374
BRANCH=None
TEST=Boot to S0, plug in a sink, verify that VBUS is sourced.
TEST=Repeat above test in other orientation.
Change-Id: I086375293206fb4179be6160ee9fc566eb140583
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057843
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'driver')
| -rw-r--r-- | driver/tcpm/raa489000.c | 3 | ||||
| -rw-r--r-- | driver/tcpm/raa489000.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/driver/tcpm/raa489000.c b/driver/tcpm/raa489000.c index 5bd72a8e13..9b4581a421 100644 --- a/driver/tcpm/raa489000.c +++ b/driver/tcpm/raa489000.c @@ -101,6 +101,9 @@ int raa489000_init(int port) regval |= RAA489000_TCPCV1_0_EN; else regval &= ~RAA489000_TCPCV1_0_EN; + + /* Allow the TCPC to control VBUS. */ + regval |= RAA489000_TCPC_PWR_CNTRL; rv = tcpc_write16(port, RAA489000_TCPC_SETTING1, regval); if (rv) CPRINTS("c%d: failed to set TCPCIv1.0 mode", port); diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h index 557c840b82..122c6eb37e 100644 --- a/driver/tcpm/raa489000.h +++ b/driver/tcpm/raa489000.h @@ -41,6 +41,7 @@ /* TCPC_SETTING_1 */ #define RAA489000_TCPCV1_0_EN BIT(0) +#define RAA489000_TCPC_PWR_CNTRL BIT(4) /* PD_PHYSICAL_SETTING_1 */ #define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9) |