diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-08-27 18:37:12 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-31 20:21:27 +0000 |
| commit | a7370241e9f5f857d3460ef711dae4d3c5d43f0e (patch) | |
| tree | e2ce4d0962e05be61f55642b387fd3d5951da2f5 /driver | |
| parent | 4ecdf5b0928255cf6c0a847aab88058760870c79 (diff) | |
| download | chrome-ec-a7370241e9f5f857d3460ef711dae4d3c5d43f0e.tar.gz | |
STT: Don't talk to the SoC outside S0
STT interface is not available outside of S0, so report that the
interface is not powered and allow the STT hook to exit quickly in this
condition.
BRANCH=None
BUG=b:197745639
TEST=No STT errors with board in G3 state
Change-Id: Id0c926ce896cdb4d3096746b3e7cc99db83bdd2d
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3126700
Tested-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'driver')
| -rw-r--r-- | driver/amd_stt.c | 5 | ||||
| -rw-r--r-- | driver/sb_rmi.c | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/driver/amd_stt.c b/driver/amd_stt.c index b8ac8dcfba..90fd82523b 100644 --- a/driver/amd_stt.c +++ b/driver/amd_stt.c @@ -5,6 +5,7 @@ #include "amd_stt.h" #include "common.h" +#include "chipset.h" #include "console.h" #include "driver/sb_rmi.h" #include "hooks.h" @@ -72,6 +73,10 @@ static void amd_stt_handler(void) int soc_temp_mk; int ambient_temp_mk; + /* STT interface is only active in S0 */ + if (!chipset_in_state(CHIPSET_STATE_ON)) + return; + /* * TODO(b/192391025): Replace with temp_sensor_read_mk(TEMP_SENSOR_SOC) */ diff --git a/driver/sb_rmi.c b/driver/sb_rmi.c index 448e149456..fbcbd990ff 100644 --- a/driver/sb_rmi.c +++ b/driver/sb_rmi.c @@ -6,6 +6,7 @@ /* AMD SB-RMI (Side-band Remote Management Interface) Driver */ #include "common.h" +#include "chipset.h" #include "i2c.h" #include "sb_rmi.h" #include "stdbool.h" @@ -90,6 +91,10 @@ int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr) int val; bool alerted; timestamp_t start; + + if (!chipset_in_state(CHIPSET_STATE_ON)) + return EC_ERROR_NOT_POWERED; + /** * Step 1: writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F) to * indicate that command is to be serviced and to make sure |