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| author | Devin Lu <Devin.Lu@quantatw.com> | 2022-03-28 11:55:20 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-14 05:21:57 +0000 |
| commit | 88a19dd1b569d6c96db2bc0214eeb2f86c86f5de (patch) | |
| tree | 2841078e149dfef8ece95c3c33afb9704cb1f2d0 /driver | |
| parent | 37d45dd56cbf7f0b9d54b2012eab7c218d4f19b1 (diff) | |
| download | chrome-ec-88a19dd1b569d6c96db2bc0214eeb2f86c86f5de.tar.gz | |
anahera: Tune USBA retimer EQ revision 2
Tune USBA retimer EQ for USB A0, USB A1 port.
BUG=b:203837657
BRANCH=none
TEST=i2cxfer to read setting is correct.
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Change-Id: Ib29f17b8b54a9ea8a4915a5c889b589bf7e62c53
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3555329
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'driver')
| -rw-r--r-- | driver/retimer/ps8811.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/driver/retimer/ps8811.h b/driver/retimer/ps8811.h index a0ab50e5d7..5721f31eae 100644 --- a/driver/retimer/ps8811.h +++ b/driver/retimer/ps8811.h @@ -138,6 +138,25 @@ #define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4) #define PS8811_CHAN_A_SWING_SHIFT 4 +#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73 +#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1) +#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1 +#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06 + +#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 + #define PS8811_REG1_USB_CHAN_B_SWING 0xA4 #define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0) #define PS8811_CHAN_B_SWING_SHIFT 0 |