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| author | Caveh Jalali <caveh@chromium.org> | 2021-04-14 20:36:26 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-08 00:03:36 +0000 |
| commit | b13c43122703c62eaf8e3016c9ba04a1993096f0 (patch) | |
| tree | 40a8ce2b3093d189e72645f5bbb3a54240539593 /driver | |
| parent | e567154e617dbe75c9a1e8dd7904b0846bd51f68 (diff) | |
| download | chrome-ec-b13c43122703c62eaf8e3016c9ba04a1993096f0.tar.gz | |
ps8xxx: Add FRS support via ps8815 TCPC
This enables FRS (fast role swap) support on the ps8815. When FRS is
enabled, one of the ps8815 GPIOs is used to control FRS on the PPC.
BRANCH=none
BUG=b:183127346
TEST=buidlall passes.
verified cablematters HDMI HUB stays powered when A/C is removed.
Change-Id: I949958e51512b096e55d405de9fc7db848e58ceb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2827951
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'driver')
| -rw-r--r-- | driver/tcpm/ps8xxx.c | 42 | ||||
| -rw-r--r-- | driver/tcpm/ps8xxx.h | 5 |
2 files changed, 47 insertions, 0 deletions
diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c index ef6f37263a..b19384f2a2 100644 --- a/driver/tcpm/ps8xxx.c +++ b/driver/tcpm/ps8xxx.c @@ -728,6 +728,27 @@ static int ps8xxx_enter_low_power_mode(int port) } #endif +__maybe_unused static int ps8815_tcpc_fast_role_swap_enable(int port, + int enable) +{ + int status; + + if (!tcpm_tcpc_has_frs_control(port)) + return EC_SUCCESS; + + /* + * TODO(b/183127346): Confirm register write order + */ + status = tcpc_update8(port, + PS8815_P1_REG_RESERVED_F4, + PS8815_P1_REG_RESERVED_F4_FRS_EN, + enable ? MASK_SET : MASK_CLR); + if (status != EC_SUCCESS) + return status; + + return tcpci_tcpc_fast_role_swap_enable(port, enable); +} + static int ps8xxx_dci_disable(int port) { int i; @@ -819,6 +840,24 @@ static int ps8xxx_tcpm_init(int port) status = ps8815_disable_rp_detect_workaround_check(port); if (status != EC_SUCCESS) return status; + + /* + * NOTE(b/183127346): Enable FRS sequence: + * + * one-time chip config: + * set reg 0xd1.FRS_EN: enable FRS without waiting for CC + * on FRS device detect: + * set reg POWER_CTRL.FRS_ENABLE + * set reg 0xf4.FRS_EN (drive FRS GPIO to PPC) + */ + if (tcpm_tcpc_has_frs_control(port)) { + status = tcpc_update8(port, + PS8815_P1_REG_RESERVED_D1, + PS8815_P1_REG_RESERVED_D1_FRS_EN, + MASK_SET); + if (status != EC_SUCCESS) + return status; + } } board_ps8xxx_tcpc_init(port); @@ -954,6 +993,9 @@ const struct tcpm_drv ps8xxx_tcpm_drv = { .enter_low_power_mode = ps8xxx_enter_low_power_mode, #endif .set_bist_test_mode = tcpci_set_bist_test_mode, +#if defined(CONFIG_USB_PD_FRS) && defined(CONFIG_USB_PD_TCPM_PS8815) + .set_frs_enable = ps8815_tcpc_fast_role_swap_enable, +#endif }; #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index 508f185ef3..f7d0cacbf0 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -68,6 +68,11 @@ #define PS8815_REG_APTX_EQ_AT_5G 0x24 #define PS8815_REG_RX_EQ_AT_5G 0x26 +#define PS8815_P1_REG_RESERVED_D1 0xD1 +#define PS8815_P1_REG_RESERVED_D1_FRS_EN BIT(7) +#define PS8815_P1_REG_RESERVED_F4 0xF4 +#define PS8815_P1_REG_RESERVED_F4_FRS_EN BIT(6) + /* * Below register is defined from Parade PS8815 Register Table, * See b:189587527 for more detail. |