cr50: Consolidate CCD device enable

Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage
their own enabling and disabling of the ports (UART, SPI, etc.)  This
is tricky because the rules for when ports should be enabled are
non-trivial and must be applied in the correct order.  In additionl
the changes all need to be serialized, so that the hardware ends up in
the correct state even if multiple state machines are changing
simultaneously.

Consolidate all of that into chip/g/rdd.c.  The debug command for it
is now 'ccdstate', which just prints the state machines.  This will
allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd
open', etc.

Also include UART bit-banging into that state which must be
consistent.  Previously, it was possible for bit-banging to leave UART
TX connected, instead of returning it to the previous state.

Use better names for CCD config fields for UART.  I'd had them backwards.

BUG=b:62537474
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 image
	1) No servo or CCD
	Pull SERVO_DETECT low (disconnected)
	Pull CCD_MODE_L high (disabled)
	Pull EC_DETECT and AP_DETECT high (on)
	Reboot.  RX is enabled even if cables are disconnected so we buffer.
	ccdstate -> UARTAP UARTEC

	Pull EC_DETECT low.
	ccdstate -> UARTAP

	Pull EC_DETECT high and AP_DETECT low.
	ccdstate -> UARTEC
	Pull AP_DETECT high.
	ccdstate -> UARTAP UARTEC

	2) Servo only still allows UART RX
	Pull SERVO_DETECT high (connected).
	ccdstate -> UARTAP UARTEC

	3) Both servo and CCD prioritizes servo.
	Pull CCD_MODE_L low (enabled).
	ccdstate -> UARTAP UARTEC

	Reboot, to make sure servo wins at boot time.
	ccdstate -> UARTAP UARTEC

	Bit-banging doesn't work when servo is connected.
	bitbang 2 9600 even -> superseded by servo
	bitbang -> disabled
	ccdstate -> UARTAP UARTEC

	4) CCD only allows more ports and remembers we wanted to bit-bang
	Pull SERVO_DETECT low.
	ccdstate --> UARTAP+TX UARTEC+BB I2C SPI
	bitbang 2 disable
	ccdstate --> UARTAP+TX UARTEC+TX I2C SPI

	Reboot and see we don't take over servo ports until we're
	sure servo isn't present.
	ccdstate --> UARTAP UARTEC (for first second)
	ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that)

	5) Bit-banging takes over ECTX
	bitbang 2 9600 even
	bitbang -> baud rate 9600, parity even
	ccdstate -> UARTAP+TX UARTEC+BB I2C SPI

	bitbang 2 disable
	ccdstate -> UARTAP+TX UARTEC+TX I2C SPI

	6) Permissions work.  Allow easy access to full console and ccdopen:
	ccdset OpenNoTPMWipe always
	ccdset OpenNoLongPP always
	ccdset GscFullConsole always

	Default when locked is full AP UART EC RO, no I2C or SPI
	ccdlock
	ccdstate -> UARTAP+TX UARTEC

	No EC transmit permission means no bit-banging
	bitbang 2 9600 even
	bitbang -> disabled
	ccdstate -> UARTAP+TX UARTEC

	But it remembers that we wanted to
	ccdopen
	ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
	bitbang 2 disable
	ccdstate -> UARTAP+TX UARTEC+TX I2C SPI

	Try turning on/off permissions
	ccdset UartGscTxECRx always
	ccdlock
	ccdstate -> UARTAP+TX UARTEC+TX

	No read means no write either
	ccdset UartGscRxECTx ifopened
	ccdlock
	ccdstate -> UARTAP+TX
	ccdopen
	ccdset UartGscRXAPTx ifopened
	ccdlock
	ccdstate -> (nothing)

	Check AP transmit permissions too
	ccdopen
	ccdset UartGscRxAPTx always
	ccdset UartGscTxAPRx ifopened
	ccdlock
	ccdstate -> UARTAP

	Check I2C
	ccdopen
	ccdset I2C always
	ccdlock
	ccdstate -> UARTAP I2C

	SPI port is enabled if either EC or AP flash is allowed
	ccdopen
	ccdset flashap always
	ccdlock
	ccdstate -> UARTAP I2C SPI
	ccdopen
	ccdset flashec always
	ccdset flashap ifopened
	ccdlock
	ccdstate -> UARTAP I2C SPI

	Back to defaults
	ccdoops

Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/615928
Reviewed-by: Mary Ruthven <mruthven@chromium.org>

1 files changed, 9 insertions, 9 deletions

diff --git a/include/case_closed_debug.h b/include/case_closed_debug.h
index 35322c5cf7..eb441327a7 100644
--- a/include/case_closed_debug.h
+++ b/include/case_closed_debug.h
@@ -96,11 +96,11 @@ enum ccd_flag {
 
 /* Capabilities */
 enum ccd_capability {
-	/* AP and EC UART output (from AP/EC) and input (to AP/EC) */
-	CCD_CAP_AP_TX_CR50_RX = 0,
-	CCD_CAP_AP_RX_CR50_TX = 1,
-	CCD_CAP_EC_TX_CR50_RX = 2,
-	CCD_CAP_EC_RX_CR50_TX = 3,
+	/* UARTs to/from AP and EC */
+	CCD_CAP_GSC_RX_AP_TX = 0,
+	CCD_CAP_GSC_TX_AP_RX = 1,
+	CCD_CAP_GSC_RX_EC_TX = 2,
+	CCD_CAP_GSC_TX_EC_RX = 3,
 
 	/* Access to AP SPI flash */
 	CCD_CAP_AP_FLASH = 4,
@@ -114,8 +114,8 @@ enum ccd_capability {
 	/* Reboot EC or AP */
 	CCD_CAP_REBOOT_EC_AP = 7,
 
-	/* Cr50 restricted console commands */
-	CCD_CAP_CR50_RESTRICTED_CONSOLE = 8,
+	/* GSC restricted console commands */
+	CCD_CAP_GSC_RESTRICTED_CONSOLE = 8,
 
 	/* Allow ccd-unlock or ccd-open without AP reboot */
 	CCD_CAP_UNLOCK_WITHOUT_AP_REBOOT = 9,
@@ -132,8 +132,8 @@ enum ccd_capability {
 	/* Allow removing the battery to bypass physical presence requirement */
 	CCD_CAP_REMOVE_BATTERY_BYPASSES_PP = 13,
 
-	/* Allow Cr50 firmware update without wiping TPM data */
-	CCD_CAP_CR50_FW_UPDATE_WITHOUT_TPM_WIPE = 14,
+	/* Allow GSC firmware update without wiping TPM data */
+	CCD_CAP_GSC_FW_UPDATE_WITHOUT_TPM_WIPE = 14,
 
 	/* Access to I2C via USB */
 	CCD_CAP_I2C = 15,