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authorWai-Hong Tam <waihong@google.com>2018-04-21 11:06:51 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-05-08 13:17:13 -0700
commit71e966af61f3e4b23e658f42552938c9d6941228 (patch)
treea274871e29466717adee085ba9b02973f88f7333 /include/chipset.h
parent139b84f5b0ed20bc14ce76cb5e2e16a11165b3bd (diff)
downloadchrome-ec-71e966af61f3e4b23e658f42552938c9d6941228.tar.gz
cheza: Enable AP_RST_REQ as a request from AP to reset itself
This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising edge interrupts to trigger a hook to call chipset_reset(). As the hook task will be preempted by the chipset task, it adds a flag bypass_power_lost_trigger to avoid triggering to S5 as the chipset state machines sees power lost during the reset. So far the chipset_reset() implementation is to do a cold reset; will be revised to a warm reset after the PMIC registers are reprogrammed. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran 'reboot' on AP console which toggles the GPIO. Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1023986 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'include/chipset.h')
-rw-r--r--include/chipset.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/chipset.h b/include/chipset.h
index ba78c45397..85d33425f8 100644
--- a/include/chipset.h
+++ b/include/chipset.h
@@ -121,4 +121,12 @@ int chipset_pltrst_is_valid(void) __attribute__((weak));
* Execute chipset-specific reboot.
*/
void chipset_handle_reboot(void);
+
+/**
+ * GPIO interrupt handler of reset request from AP.
+ *
+ * It is used in SDM845 chipset power sequence.
+ */
+void chipset_reset_request_interrupt(enum gpio_signal signal);
+
#endif /* __CROS_EC_CHIPSET_H */