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| author | Jun Lin <CHLin56@nuvoton.com> | 2021-04-29 14:31:33 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-04 02:39:08 +0000 |
| commit | 14dd51f4fcfeb1bbbdbf0dd9f9365c4072db44ef (patch) | |
| tree | 196ceee7688b398a4796f5fce2cfe2195e38c29b /include/config.h | |
| parent | af432dbd2c5ba0e979549b4b9bad8edbf414bda3 (diff) | |
| download | chrome-ec-14dd51f4fcfeb1bbbdbf0dd9f9365c4072db44ef.tar.gz | |
Port80: allow to accept 4-byte Port80 code
The original Port80 implementation assumes that the Port80 code is
only 2-byte wide and is less than 0x100. In the recent AMD chipset
(CEZANNE), AP will send a 4-byte Port80 code via a single PUT_IOWR_SHORT
eSPI transaction in PSP. This CL adds a config option to allow the
Port80 to print 4-byte code when the config is defined.
BRANCH=none
BUG=b:184872297
TEST=build the image with "#define CONFIG_PORT80_4_BYTE";
connect npcx9_evb to the eSPI host emulator; the host sends a
PUT_IOWR_SHORT transaction to IO address 0x80 with 4 bytes of code
"0xEEE20400"; the EC console shows:
Port 80 writes:
eee20400 <--new
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I3b93d9fc41e1875bb628a15c58231005e9555cfd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2858296
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'include/config.h')
| -rw-r--r-- | include/config.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/config.h b/include/config.h index 8dc2d0aa5a..b6f48c741a 100644 --- a/include/config.h +++ b/include/config.h @@ -3270,6 +3270,12 @@ */ #define CONFIG_PORT80_PRINT_IN_INT 0 +/* + * Allow Port80 common layer to dump 4-byte Port80 code. This is only supported + * on NPCX9 (and latter) chips. + */ +#undef CONFIG_PORT80_4_BYTE + /* MAX695x 7 segment driver */ #undef CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY |