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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-05-11 14:23:31 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-15 06:42:30 +0000 |
| commit | e3dce49334a2b44e337744bc719a27c63261f35e (patch) | |
| tree | 3ee485350fafffaf53206036a3a19184068feeb5 /include/config_std_internal_flash.h | |
| parent | cba37a13d2342e4c81b0be3c84010baf3d846162 (diff) | |
| download | chrome-ec-e3dce49334a2b44e337744bc719a27c63261f35e.tar.gz | |
cleanup: Use appropriate image geometry CONFIGs
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Diffstat (limited to 'include/config_std_internal_flash.h')
| -rw-r--r-- | include/config_std_internal_flash.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h new file mode 100644 index 0000000000..c0df3d4199 --- /dev/null +++ b/include/config_std_internal_flash.h @@ -0,0 +1,38 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H +#define __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H + +/* + * Standard memory-mapped flash layout: + * - RO image starts at the beginning of flash. + * - PSTATE immediately follows the RO image. + * - RW image starts at the second half of flash. + * - WP region consists of the first half of flash (RO + PSTATE). + */ + +/* + * The EC uses the one bank of flash to emulate a SPI-like write protect + * register with persistent state. + */ +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) + +/* Size of one firmware image in flash */ +#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2) +#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE + +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_RW_STORAGE_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE + +#define CONFIG_WP_OFF CONFIG_RO_STORAGE_OFF +#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE + +#endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */ |