diff options
| author | David Huang <david.huang@quanta.corp-partner.google.com> | 2023-03-17 09:19:45 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-03-20 04:12:43 +0000 |
| commit | 441ba1e1d063ff0bf8befd7055adf77a1e05794c (patch) | |
| tree | 9b54bbb2e9f6c3f9ef381fa862f3ccb325d80752 /include/driver/pse_ltc4291.h | |
| parent | ef44ebdc0a74ddca5b8cf9722f0afe0cf858b70e (diff) | |
| download | chrome-ec-441ba1e1d063ff0bf8befd7055adf77a1e05794c.tar.gz | |
common: Move pse driver into driver place
Since there are more projects using this driver.
Move it into driver place.
BUG=b:273191751
BRANCH=None
TEST=make buildall -j
Change-Id: I50e2cb480a551ce19722edc2b6f70824f4b9147e
Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4335461
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'include/driver/pse_ltc4291.h')
| -rw-r--r-- | include/driver/pse_ltc4291.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/include/driver/pse_ltc4291.h b/include/driver/pse_ltc4291.h new file mode 100644 index 0000000000..4db9ac4998 --- /dev/null +++ b/include/driver/pse_ltc4291.h @@ -0,0 +1,60 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * The LTC4291 is a power over ethernet (PoE) power sourcing equipment (PSE) + * controller. + */ + +#include "i2c.h" +#include "timer.h" +#include "util.h" + +#define LTC4291_I2C_ADDR 0x2C + +#define LTC4291_REG_SUPEVN_COR 0x0B +#define LTC4291_REG_STATPWR 0x10 +#define LTC4291_REG_STATPIN 0x11 +#define LTC4291_REG_OPMD 0x12 +#define LTC4291_REG_DISENA 0x13 +#define LTC4291_REG_DETENA 0x14 +#define LTC4291_REG_DETPB 0x18 +#define LTC4291_REG_PWRPB 0x19 +#define LTC4291_REG_RSTPB 0x1A +#define LTC4291_REG_ID 0x1B +#define LTC4291_REG_DEVID 0x43 +#define LTC4291_REG_HPMD1 0x46 +#define LTC4291_REG_HPMD2 0x4B +#define LTC4291_REG_HPMD3 0x50 +#define LTC4291_REG_HPMD4 0x55 +#define LTC4291_REG_LPWRPB 0x6E + +#define LTC4291_FLD_STATPIN_AUTO BIT(0) +#define LTC4291_FLD_RSTPB_RSTALL BIT(4) + +#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) +#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) +#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) +#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) + +#define LTC4291_OPMD_AUTO 0xFF +#define LTC4291_DISENA_ALL 0x0F +#define LTC4291_DETENA_ALL 0xFF +#define LTC4291_ID 0x64 +#define LTC4291_DEVID 0x38 +#define LTC4291_HPMD_MIN 0x00 +#define LTC4291_HPMD_MAX 0xA8 + +#define LTC4291_PORT_MAX 4 + +#define LTC4291_RESET_DELAY_US (20 * MSEC) + +#define I2C_PSE_READ(reg, data) \ + i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) + +#define I2C_PSE_WRITE(reg, data) \ + i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) + +extern const int pse_port_hpmd[LTC4291_PORT_MAX]; |